Ao Zhong has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48010 )
Change subject: doc/mb/hp/z220_sff.md: Add some information ......................................................................
doc/mb/hp/z220_sff.md: Add some information
Added some test results about this mainboard and the way to disable SPI flash write protection.
Signed-off-by: Ao Zhong hacc1225@gmail.com Change-Id: I3ec61557c9c800db66b3b7db78ea6120c109d84a --- M Documentation/mainboard/hp/z220_sff.md A Documentation/mainboard/hp/z220_sff_pin1.jpg A Documentation/mainboard/hp/z220_sff_pin2.jpg 3 files changed, 43 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/48010/1
diff --git a/Documentation/mainboard/hp/z220_sff.md b/Documentation/mainboard/hp/z220_sff.md index 0dfa653..7ebe446 100644 --- a/Documentation/mainboard/hp/z220_sff.md +++ b/Documentation/mainboard/hp/z220_sff.md @@ -11,6 +11,35 @@ - Advanced LED control - Advanced power configuration in S3
+## Working + +- USB 3.0 and USB 2.0 +- S3 suspend/resume (Tested with Arch Linux 2020.11.25 and resume with power button) +- SATA +- Onboard audio +- Front headphone jack +- Rear headphone jack +- Internal audio speaker +- Onboard network (Working with Gigabit Ethernet Firmware blob) +- PCIe x16 Gen3 (Tested with Nvidia Quadro 600) +- PCIe x4 Gen2 / x16 connector (Tested with WD SN550 SSD) +- Boot from NVMe SSD (Tested with Tianocore, M.2-to-PCIe adapter and WD SN550 SSD) +- CPU Temp sensors (Tested with lm-sensors in Arch Linux) +- Native raminit (Tested with Xeon-E3 1240v2, 4x4G Hynix ECC DDR3 RAM) +- Automatic fan control +- 1x PCIe GPU in PCIe x16 Gen3 slot (Tested with Nvidia Quadro 600) +- using `me_cleaner` +- using `flashrom` + +## Untested + +- Integrated graphics +- PS/2 port +- TPM +- Parallel port +- PCI slot +- PCIe x1 gen2 slot + ## Flashing coreboot
```eval_rst @@ -39,6 +68,20 @@
The SPI flash can be accessed using [flashrom].
+When you flash from stock firmware, you may need to short ME/AMT flash override pins to make the whole SPI flash accessible. + +**Position of ME/AMT flash override pins** + +![][z220_sff_pin1] + +[z220_sff_pin1]: z220_sff_pin1.jpg + +**Closeup view of ME/AMT flash override pins** + +![][z220_sff_pin2] + +[z220_sff_pin2]: z220_sff_pin2.jpg + ### External programming
External programming with an SPI adapter and [flashrom] does work, but it powers the diff --git a/Documentation/mainboard/hp/z220_sff_pin1.jpg b/Documentation/mainboard/hp/z220_sff_pin1.jpg new file mode 100644 index 0000000..b20a475 --- /dev/null +++ b/Documentation/mainboard/hp/z220_sff_pin1.jpg Binary files differ diff --git a/Documentation/mainboard/hp/z220_sff_pin2.jpg b/Documentation/mainboard/hp/z220_sff_pin2.jpg new file mode 100644 index 0000000..dfe8ad5 --- /dev/null +++ b/Documentation/mainboard/hp/z220_sff_pin2.jpg Binary files differ