Attention is currently required from: Michael Niewöhner, Patrick Rudolph. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52627 )
Change subject: soc/intel/skylake: Clean up root port structs ......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52627/comment/47381482_e68f1d3a PS2, Line 9: correct struct with : root port count
PCIe root port groups struct?
Done
File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/52627/comment/7887fc6f_10b56cf2 PS2, Line 35: static const struct pcie_rp_group pch_rp_groups[] = { : #if CONFIG(SKYLAKE_SOC_PCH_H) : { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, : { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 }, : /* Sunrise Point PCH-H actually only has 4 ports in the : third group. But that would require a runtime check : and probing 4 non-existent ports shouldn't hurt. */ : { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 }, : #else : { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, : { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, : #endif :
we already have one PCH with only 4 ports in group 3 (PCIE_2): KBL. […]
I don't think we should do it like that because it makes things even more confusing.