[coreboot-gerrit] Change in coreboot[master]: google/trogdor: Remove RO_FSG region

[Julius Werner (Code Review)]

Hello Philip Chen,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/41980

to review the following change.

Change subject: google/trogdor: Remove RO_FSG region
......................................................................

google/trogdor: Remove RO_FSG region

We decided to store the FSG on eMMC instead of SPI flash, so we don't
need this region anymore. Getting rid of it allows us to put more space
into CBFS (to store hi-res bitmaps). Also grow VPD by some remaining
amount to keep the FMAP alignment reasonable.

Signed-off-by: Julius Werner 
Change-Id: If73450b65718affae71b6ada70ded5c5f45cfb4c
---
M src/mainboard/google/trogdor/chromeos.fmd
1 file changed, 3 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/41980/1

diff --git a/src/mainboard/google/trogdor/chromeos.fmd b/src/mainboard/google/trogdor/chromeos.fmd
index 2f93712..3aa0473 100644
--- a/src/mainboard/google/trogdor/chromeos.fmd
+++ b/src/mainboard/google/trogdor/chromeos.fmd
@@ -2,17 +2,16 @@

FLASH@0x0 8M {
    WP_RO 4M {
-		RO_SECTION 0x204000 {
+		RO_SECTION 0x3c4000 {
    		BOOTBLOCK 96K
    		COREBOOT(CBFS)
-			FMAP@0x200000 0x1000
+			FMAP@0x3c0000 0x1000
    		GBB 0x2f00
    		RO_FRID 0x100
    	}
-		RO_VPD(PRESERVE) 16K
+		RO_VPD(PRESERVE) 228K
    	RO_DDR_TRAINING(PRESERVE) 8K
    	RO_LIMITS_CFG(PRESERVE) 4K
-		RO_FSG(PRESERVE)
    }

RW_VPD(PRESERVE) 32K