[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Speed up postcar loading using intermediate cac...

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34791 )

Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching
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Patch Set 10:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34791/9/src/soc/intel/cannonlake/ro... 
File src/soc/intel/cannonlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/34791/9/src/soc/intel/cannonlake/ro... 
PS9, Line 167: 	/* Cache the ROM as WP just below 4GiB. */
> yes, ramstage execution will help for sure. […]

You ** NEED ** to make the perfomance comparison with TSEG marked WB. Please provide the actual output of cbmem -t (or -T) somewhere. Otherwise the 4 milliseconds you advertise in your commit message is just bogus number.