Paul Menzel (paulepanter@users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5564
-gerrit
commit e25733f79b485fc405b8f72eb475e7fb18b45d51 Author: Paul Menzel paulepanter@users.sourceforge.net Date: Mon Apr 21 23:20:44 2014 +0200
vendorcode/amd/agesa/f14/Makefile.inc: Use `btver1` for `march` switch
From chapter 3.17.17 of the GCC manual [1]:
‘btver1’ CPUs based on AMD Family 14h cores with x86-64 instruction set support. (This supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit instruction set extensions.)
RAM stage on the ASRock E350M1 is eleven bytes bigger with gcc-4.8.real (Debian 4.8.2-19) 4.8.2.
$ cbfstool build/coreboot.rom print […] Name Offset Type Size cmos_layout.bin 0x0 cmos_layout 1776 pci1002,9802.rom 0x740 optionrom 65536 fallback/romstage 0x10780 stage 321708 - fallback/coreboot_ram 0x5f080 stage 195854 + fallback/coreboot_ram 0x5f080 stage 195865 fallback/payload 0x8ee00 payload 51782 config 0x9b880 raw 3858 (empty) 0x9c7c0 null 3552152
[1] http://gcc.gnu.org/onlinedocs/gcc/i386-and-x86-64-Options.html#i386-and-x86-... 3.17.17 Intel 386 and AMD x86-64 Options
Change-Id: I0139df7a0b9157bce55cdb1cfe5f93c6314699be Signed-off-by: Paul Menzel paulepanter@users.sourceforge.net --- src/vendorcode/amd/agesa/f14/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index 2e7853c..6db88a3 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -62,7 +62,7 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/GNB AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/CPU AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/Mem
-AGESA_CFLAGS =-march=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing +AGESA_CFLAGS =-march=btver1 -fno-zero-initialized-in-bss -fno-strict-aliasing
export AGESA_ROOT := $(AGESA_ROOT) export AGESA_INC := $(AGESA_INC)