[coreboot-gerrit] [S] Change in coreboot[master]: soc/intel/alderlake/vr_config.c: Fix GT domain TDC current

[Michał Żygowski (Code Review)]

Attention is currently required from: Sumeet Pawnikar, Tarun Tuli, Subrata Banik, Michał Kopeć, Krystian Hebel, Vidya Gopalakrishnan.

Hello Sumeet Pawnikar, build bot (Jenkins), Tarun Tuli, Subrata Banik, Michał Kopeć, Krystian Hebel, Vidya Gopalakrishnan,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/72998

to look at the new patch set (#2).

Change subject: soc/intel/alderlake/vr_config.c: Fix GT domain TDC current
......................................................................

soc/intel/alderlake/vr_config.c: Fix GT domain TDC current

Alder Lake-S 2+0 SKUs and 35W SKUs have 20A GT TDC, all other Alder
Lake-S SKUs have GT TDC of 22A.

Based on the default settings of ADL-S FSP.

Signed-off-by: Michał Żygowski 
Change-Id: Ie6851d322fc9354d019a76503c3d35b5e6eca48b
---
M src/soc/intel/alderlake/vr_config.c
1 file changed, 30 insertions(+), 15 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/72998/2