Attention is currently required from: Ravi kumar, Shelley Chen, mturney mturney, Julius Werner. Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47284 )
Change subject: sc7280: support bitbang UART w/gpio ......................................................................
Patch Set 34:
(3 comments)
File src/soc/qualcomm/sc7280/Kconfig:
https://review.coreboot.org/c/coreboot/+/47284/comment/2073c630_8084b6ea PS5, Line 14: select CACHE_MRC_SETTINGS
Is this needed for UART config? Maybe we can move this to another more relevant CL to make this one […]
if we deleted this macro getting build errors. i keep this change as it is.
File src/soc/qualcomm/sc7280/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/47284/comment/c68bf2ec_d9908241 PS5, Line 9: bootblock-$(CONFIG_SC7280_QSPI) += qspi.c : bootblock-y += clock.c : bootblock-y += gpio.c : bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c
Since these are being added to all stages, please use the "all-y +=" syntax.
Ack
File src/soc/qualcomm/sc7280/uart_bitbang.c:
https://review.coreboot.org/c/coreboot/+/47284/comment/810df6ec_e162a385 PS5, Line 7: #define UART_TX_PIN GPIO(44)
as per internal hardware schematic reference manual for console tx gpio is 44.
Done