[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel: Fix slp-s0 residency counter frequency LPIT table

[Sukumar Ghorai (Code Review)]

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Lance Zhao, Subrata Banik, Tarun, Tim Wawrzynczak.

Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78164?usp=email )

Change subject: soc/intel: Fix slp-s0 residency counter frequency LPIT table
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Patch Set 11:

(2 comments)

File src/soc/intel/common/block/acpi/lpit.c:

https://review.coreboot.org/c/coreboot/+/78164/comment/a567aa15_4c3bd882 :
PS3, Line 34: MSR value return in usec
> Ref. https://uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_Idle.... Sec 2.2. […]

Acknowledged

https://review.coreboot.org/c/coreboot/+/78164/comment/f71e4352_5e285570 :
PS3, Line 34: 0;
> MSR 0x632 is for all Intel Core SoCs Package C-10 entry counter and give is mico-sec and hence we mu […]

Acknowledged