[coreboot-gerrit] Change in coreboot[master]: cpu/intel/haswell: Do not set PMG_IO_CAPTURE_BASE MSR

[Nico Huber (Code Review)]

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46917 )

Change subject: cpu/intel/haswell: Do not set PMG_IO_CAPTURE_BASE MSR
......................................................................

cpu/intel/haswell: Do not set PMG_IO_CAPTURE_BASE MSR

The MSR only needs to be set when IO MWAIT redirection is to be enabled.
This was copied from Sandy Bridge, which already had this inconsistency.

Change-Id: I424333afd654db9a7e180e9a2c31d369e3d92fd6
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46917
Reviewed-by: Nico Huber 
Tested-by: build bot (Jenkins) 
---
M src/cpu/intel/haswell/haswell_init.c
1 file changed, 0 insertions(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 44bbbfd..ff9573f 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -446,12 +446,6 @@
    /* The deepest package c-state defaults to factory-configured value. */
    wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);

-	msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE);
-	msr.lo &= ~0xffff;
-	msr.lo |= (get_pmbase() + 0x14);	// LVL_2 base address
-	/* The deepest package c-state defaults to factory-configured value. */
-	wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr);
-
    msr = rdmsr(MSR_MISC_PWR_MGMT);
    msr.lo &= ~(1 << 0);	// Enable P-state HW_ALL coordination
    wrmsr(MSR_MISC_PWR_MGMT, msr);