[coreboot-gerrit] Change in coreboot[master]: mb/ocp/deltalake: Fix SMBIOS type 9 bugs

[Johnny Lin (Code Review)]

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58100 )

Change subject: mb/ocp/deltalake: Fix SMBIOS type 9 bugs
......................................................................

mb/ocp/deltalake: Fix SMBIOS type 9 bugs

1. Fix PCIe slot capabilities was not really read from an IIO root port
   device. The Hot-Plug capability of IIO root port cannot be enabled due
   to FSP limitation, but the code should reflect the true capabilities by
   reading the root port device's CSR.
2. Clear the flag before the next for-loop iteration.

Tested=On OCP Delta Lake, dmidecode -t 9 shows expected results.

Change-Id: Iea437cdf3da5410b6b7a749a1be970f0948d92d9
Signed-off-by: Johnny Lin 
---
M src/mainboard/ocp/deltalake/ramstage.c
1 file changed, 12 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/58100/1

diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c
index 8d9de82..cdcfe83 100644
--- a/src/mainboard/ocp/deltalake/ramstage.c
+++ b/src/mainboard/ocp/deltalake/ramstage.c
@@ -198,7 +198,7 @@
    uint8_t characteristics_2 = 0;
    uint32_t vendor_device_id;
    uint8_t stack_busnos[MAX_IIO_STACK];
-	pci_devfn_t pci_dev;
+	pci_devfn_t pci_dev_slot, pci_dev = 0;
    unsigned int cap;
    uint16_t sltcap;

@@ -251,14 +251,14 @@
    	else
    		slot_length = SlotLengthShort;

-		pci_dev = PCI_DEV(stack_busnos[slotinfo[index].stack],
+		pci_dev_slot = PCI_DEV(stack_busnos[slotinfo[index].stack],
    		slotinfo[index].dev_func >> 3, slotinfo[index].dev_func & 0x7);
-		sec_bus = pci_s_read_config8(pci_dev, PCI_SECONDARY_BUS);
+		sec_bus = pci_s_read_config8(pci_dev_slot, PCI_SECONDARY_BUS);

if (sec_bus == 0xFF) {
    		slot_usage = SlotUsageUnknown;
    	} else {
-			/* Checking for Slot device availability */
+			/* Checking for downstream device availability */
    		pci_dev = PCI_DEV(sec_bus, 0, 0);
    		vendor_device_id = pci_s_read_config32(pci_dev, 0);
    		if (vendor_device_id == 0xFFFFFFFF)
@@ -269,13 +269,16 @@

characteristics_1 |= SMBIOS_SLOT_3P3V; // Provides33Volts
    	characteristics_2 |= SMBIOS_SLOT_PME; // PmeSiganalSupported
-
-		cap = pci_s_find_capability(pci_dev, PCI_CAP_ID_PCIE);
-		sltcap = pci_s_read_config16(pci_dev, cap + PCI_EXP_SLTCAP);
+		/* Read IIO root port device CSR for slot capabilities */
+		cap = pci_s_find_capability(pci_dev_slot, PCI_CAP_ID_PCIE);
+		sltcap = pci_s_read_config16(pci_dev_slot, cap + PCI_EXP_SLTCAP);
    	if (sltcap & PCI_EXP_SLTCAP_HPC)
    		characteristics_2 |= SMBIOS_SLOT_HOTPLUG;

const uint16_t slot_id = index + 1;
+		/* According to SMBIOS spec, the BDF number should be the end
+		   point on the slot, for now we keep using the root port's BDF to
+		   be aligned with our UEFI reference BIOS. */
    	length += smbios_write_type9(current, handle,
    				  slotinfo[index].slot_designator,
    				  slotinfo[index].slot_type,
@@ -287,6 +290,8 @@
    				  characteristics_2,
    				  stack_busnos[slotinfo[index].stack],
    				  slotinfo[index].dev_func);
+		characteristics_1 = 0;
+		characteristics_2 = 0;
    }

return length;