[coreboot-gerrit] Change in coreboot[master]: mb/google/volteer: Enable TCSS DMA0 and DMA1 for Volteer

[John Zhao (Code Review)]

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41387 )

Change subject: mb/google/volteer: Enable TCSS DMA0 and DMA1 for Volteer
......................................................................

mb/google/volteer: Enable TCSS DMA0 and DMA1 for Volteer

This explicitly enables both of TCSS DMA0 and DMA1 controllers
from Volteer devicetree.cb setting.

BUG=:b:146624360
TEST=Built and booted on Volteer.

Signed-off-by: John Zhao 
Change-Id: I05cc9e3964d8037d433fca443be6e8d5b444bbce
---
M src/mainboard/google/volteer/variants/baseboard/devicetree.cb
1 file changed, 7 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/41387/1

diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index b689663..70f2968 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -125,8 +125,13 @@

# TCSS USB3
    register "TcssXhciEn" = "1"
+	register "TcssXdciEn" = "0"
    register "TcssAuxOri" = "0"

+	# TCSS DMA
+	register "TcssDma0En" = "1"
+	register "TcssDma1En" = "1"
+
    # DP port
    register "DdiPortAConfig" = "1"	# eDP
    register "DdiPortBConfig" = "0"
@@ -216,8 +221,8 @@
    	device pci 0a.0 off end # Crash-log SRAM		0x9A0D
    	device pci 0d.0 on  end # USB xHCI			0x9A13
    	device pci 0d.1 off end # USB xDCI (OTG)		0x9A15
-		device pci 0d.2 off end # TBT DMA0			0x9A1B
-		device pci 0d.3 off end # TBT DMA1			0x9A1D
+		device pci 0d.2 on  end # TBT DMA0			0x9A1B
+		device pci 0d.3 on  end # TBT DMA1			0x9A1D
    	device pci 0e.0 off end # VMD				0x9A0B

# From PCH EDS(576591)