[coreboot-gerrit] [M] Change in coreboot[master]: drivers/pc80/rtc/mc146818rtc.c: Add Kconfig for RTC CMOS base addresses

[Jonathon Hall (Code Review)]

Jonathon Hall has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74903 )

Change subject: drivers/pc80/rtc/mc146818rtc.c: Add Kconfig for RTC CMOS base addresses
......................................................................

drivers/pc80/rtc/mc146818rtc.c: Add Kconfig for RTC CMOS base addresses

Configure the CMOS bank I/O base addresses with
PC_CMOS_BASE_PORT_BANK* rather than hard-coding as 0x70, 0x72.  The
defaults remain the same.

Librem Mini v1/v2 has an automatic power-on setting provided by the EC
that can be configured in its BRAM bank 1.  The RTC uses the PCH CMOS,
and it is preferable not to change this in an update, as the RTC would
reset.  By configuring these addresses, we can use the PCH CMOS bank 0
and the EC BRAM bank 1.

Change-Id: Ie44e5f5191c66f44e2df8ea0ff58a860be88bfcf
Signed-off-by: Jonathon Hall 
---
M src/drivers/pc80/rtc/Kconfig
M src/drivers/pc80/rtc/mc146818rtc.c
M src/include/pc80/mc146818rtc.h
3 files changed, 47 insertions(+), 14 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/74903/1

diff --git a/src/drivers/pc80/rtc/Kconfig b/src/drivers/pc80/rtc/Kconfig
index 0d06457..7a1c398 100644
--- a/src/drivers/pc80/rtc/Kconfig
+++ b/src/drivers/pc80/rtc/Kconfig
@@ -9,3 +9,11 @@
    depends on DRIVERS_MC146818
    help
      May be useful for legacy OSes that assume its presence.
+
+config PC_CMOS_BASE_PORT_BANK0
+	hex "Base port for CMOS bank 0 index/data registers"
+	default 0x70
+
+config PC_CMOS_BASE_PORT_BANK1
+	hex "Base port for CMOS bank 1 index/data registers"
+	default 0x72
diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c
index f45a3a0..6474ecb 100644
--- a/src/drivers/pc80/rtc/mc146818rtc.c
+++ b/src/drivers/pc80/rtc/mc146818rtc.c
@@ -249,11 +249,11 @@
 {
    uint8_t index, byte;

-	index = inb(RTC_PORT(0)) & 0x80;
+	index = inb(RTC_PORT_BANK0(0)) & 0x80;
    index |= RTC_BOOT_BYTE;
-	outb(index, RTC_PORT(0));
+	outb(index, RTC_PORT_BANK0(0));

-	byte = inb(RTC_PORT(1));
+	byte = inb(RTC_PORT_BANK0(1));

if (CONFIG(SKIP_MAX_REBOOT_CNT_CLEAR)) {
    	/*
@@ -269,5 +269,5 @@
    		byte &= 0x0f;
    }

-	outb(byte, RTC_PORT(1));
+	outb(byte, RTC_PORT_BANK0(1));
 }
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index 383c41f..98ea965 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -5,10 +5,12 @@

#include <arch/io.h>
 #include <types.h>
+#include <console/console.h>

-#define RTC_BASE_PORT 0x70
+#define RTC_BASE_PORT_BANK0 (CONFIG_PC_CMOS_BASE_PORT_BANK0)
+#define RTC_BASE_PORT_BANK1 (CONFIG_PC_CMOS_BASE_PORT_BANK1)

-#define RTC_PORT(x)	(RTC_BASE_PORT + (x))
+#define RTC_PORT_BANK0(x)	(RTC_BASE_PORT_BANK0 + (x))

/* control registers - Moto names
  */
@@ -107,24 +109,27 @@

static inline unsigned char cmos_read(unsigned char addr)
 {
-	int offs = 0;
+	int port = RTC_BASE_PORT_BANK0;
    if (addr >= 128) {
-		offs = 2;
+		port = RTC_BASE_PORT_BANK1;
    	addr -= 128;
    }
-	outb(addr, RTC_BASE_PORT + offs + 0);
-	return inb(RTC_BASE_PORT + offs + 1);
+	outb(addr, port + 0);
+	uint8_t val = inb(port + 1);
+	printk(BIOS_SPEW, "%s: addr %02X at base %02X -> val %02X\n", __func__,
+		addr, port, val);
+	return val;
 }

static inline void cmos_write_inner(unsigned char val, unsigned char addr)
 {
-	int offs = 0;
+	int port = RTC_BASE_PORT_BANK0;
    if (addr >= 128) {
-		offs = 2;
+		port = RTC_BASE_PORT_BANK1;
    	addr -= 128;
    }
-	outb(addr, RTC_BASE_PORT + offs + 0);
-	outb(val, RTC_BASE_PORT + offs + 1);
+	outb(addr, port + 0);
+	outb(val, port + 1);
 }

static inline u8 cmos_disable_rtc(void)