Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/27923
Change subject: cpu/amd: Correct number of MCA banks cleared ......................................................................
cpu/amd: Correct number of MCA banks cleared
Use the value discovered in the MCG_CAP[Count] for the number of MCA status registers to clear. The generations should have the following number of banks: * Family 10h: 6 banks * Family 12h: 6 * Family 14h: 6 * Family 15h: 7 * Family 16h: 6
Change-Id: I0fc6d127a200b10fd484e051d84353cc61b27a41 Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com --- M src/cpu/amd/agesa/family12/model_12_init.c M src/cpu/amd/agesa/family14/model_14_init.c M src/cpu/amd/agesa/family15tn/model_15_init.c M src/cpu/amd/agesa/family16kb/model_16_init.c M src/cpu/amd/family_10h-family_15h/model_10xxx_init.c M src/cpu/amd/pi/00630F01/model_15_init.c M src/cpu/amd/pi/00660F01/model_15_init.c M src/cpu/amd/pi/00730F01/model_16_init.c M src/include/cpu/amd/amdfam15.h M src/include/cpu/amd/amdfam16.h M src/soc/amd/stoneyridge/cpu.c 11 files changed, 46 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/27923/1
diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c index afdfb3b..d38a8f3 100644 --- a/src/cpu/amd/agesa/family12/model_12_init.c +++ b/src/cpu/amd/agesa/family12/model_12_init.c @@ -27,6 +27,8 @@ #include <cpu/amd/multicore.h> #include <cpu/amd/amdfam12.h>
+#define MCG_CAP 0x179 +# define MCA_BANKS_MASK 0xff #define MC0_STATUS 0x401
static void model_12_init(struct device *dev) @@ -35,6 +37,7 @@
u8 i; msr_t msr; + int i num_banks;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; @@ -52,9 +55,11 @@ disable_cache();
/* zero the machine check error status registers */ + msr = rdmsr(MCG_CAP); + num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; - for (i = 0; i < 5; i++) { + for (i = 0; i < num_banks; i++) { wrmsr(MC0_STATUS + (i * 4), msr); }
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 257f81f..fc4227a 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -28,12 +28,15 @@ #include <arch/acpi.h> #include <northbridge/amd/agesa/agesa_helper.h>
+#define MCG_CAP 0x179 +# define MCA_BANKS_MASK 0xff #define MC0_STATUS 0x401
static void model_14_init(struct device *dev) { u8 i; msr_t msr; + int num_banks; int msrno; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; @@ -75,9 +78,11 @@ x86_enable_cache();
/* zero the machine check error status registers */ + msr = rdmsr(MCG_CAP); + num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; - for (i = 0; i < 6; i++) { + for (i = 0; i < num_banks; i++) { wrmsr(MC0_STATUS + (i * 4), msr); }
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index 1e0375f..d579a5a 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -35,6 +35,7 @@
u8 i; msr_t msr; + int num_banks; int msrno; unsigned int cpu_idx; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) @@ -72,9 +73,11 @@ x86_enable_cache();
/* zero the machine check error status registers */ + msr = rdmsr(MCG_CAP); + num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; - for (i = 0; i < 6; i++) { + for (i = 0; i < num_banks; i++) { wrmsr(MC0_STATUS + (i * 4), msr); }
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index 9909793..0c584f7 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -34,6 +34,7 @@
u8 i; msr_t msr; + int num_banks; int msrno; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; @@ -70,9 +71,11 @@ x86_enable_cache();
/* zero the machine check error status registers */ + msr = rdmsr(MCG_CAP); + num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; - for (i = 0; i < 6; i++) { + for (i = 0; i < num_banks; i++) { wrmsr(MC0_STATUS + (i * 4), msr); }
diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c index 61eb813..acc65e2 100644 --- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c @@ -32,6 +32,8 @@ #include <cpu/amd/multicore.h> #include <cpu/amd/msr.h>
+#define MCG_CAP 0x179 +# define MCA_BANKS_MASK 0xff #define MC0_STATUS 0x401
static inline uint8_t is_gt_rev_d(void) @@ -62,6 +64,7 @@ { u8 i; msr_t msr; + int num_banks; struct node_core_id id; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; @@ -109,9 +112,11 @@ disable_cache();
/* zero the machine check error status registers */ + msr = rdmsr(MCG_CAP); + num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; - for (i = 0; i < 5; i++) { + for (i = 0; i < num_banks; i++) { wrmsr(MC0_STATUS + (i * 4), msr); }
diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c index 592ca4f..0269a1e 100644 --- a/src/cpu/amd/pi/00630F01/model_15_init.c +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -35,6 +35,7 @@
u8 i; msr_t msr; + int num_banks; int msrno; unsigned int cpu_idx; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) @@ -69,9 +70,11 @@ x86_enable_cache();
/* zero the machine check error status registers */ + msr = rdmsr(MCG_CAP); + num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; - for (i = 0; i < 6; i++) + for (i = 0; i < num_banks; i++) wrmsr(MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */ diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c index 24c2aea..424a6c0 100644 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ b/src/cpu/amd/pi/00660F01/model_15_init.c @@ -51,6 +51,7 @@
u8 i; msr_t msr; + int num_banks; int msrno; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; @@ -81,12 +82,13 @@ x86_enable_cache();
/* zero the machine check error status registers */ + msr = rdmsr(MCG_CAP); + num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; - for (i = 0; i < 6; i++) + for (i = 0; i < num_banks; i++) wrmsr(MC0_STATUS + (i * 4), msr);
- /* Enable the local CPU APICs */ setup_lapic();
diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index b9e0185..160d6d8 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -34,6 +34,7 @@
u8 i; msr_t msr; + int num_banks; int msrno; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; @@ -66,12 +67,13 @@ x86_enable_cache();
/* zero the machine check error status registers */ + msr = rdmsr(MCG_CAP); + num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; - for (i = 0; i < 6; i++) + for (i = 0; i < num_banks; i++) wrmsr(MC0_STATUS + (i * 4), msr);
- /* Enable the local CPU APICs */ setup_lapic();
diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h index c28ec13..3095dd1 100644 --- a/src/include/cpu/amd/amdfam15.h +++ b/src/include/cpu/amd/amdfam15.h @@ -16,6 +16,8 @@ #ifndef CPU_AMD_FAM15_H #define CPU_AMD_FAM15_H
+#define MCG_CAP 0x00000179 +# define MCA_BANKS_MASK 0xff #define MC0_STATUS 0x00000401 #define MSR_SMM_BASE 0xC0010111 #define MSR_TSEG_BASE 0xC0010112 diff --git a/src/include/cpu/amd/amdfam16.h b/src/include/cpu/amd/amdfam16.h index 8d8be83..8b7503d 100644 --- a/src/include/cpu/amd/amdfam16.h +++ b/src/include/cpu/amd/amdfam16.h @@ -16,6 +16,8 @@ #ifndef CPU_AMD_FAM16_H #define CPU_AMD_FAM16_H
+#define MCG_CAP 0x00000179 +# define MCA_BANKS_MASK 0xff #define MC0_STATUS 0x00000401 #define HWCR_MSR 0xC0010015 #define NB_CFG_MSR 0xC001001f diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 6289174..7fff120 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -121,11 +121,14 @@
int i; msr_t msr; + int num_banks;
/* zero the machine check error status registers */ + msr = rdmsr(MCG_CAP); + num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; - for (i = 0 ; i < 6 ; i++) + for (i = 0 ; i < num_banks ; i++) wrmsr(MC0_STATUS + (i * 4), msr);
setup_lapic();