[coreboot-gerrit] Change in coreboot[master]: soc/intel/elkhartlake: Lock PAM registers in finalize

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57185 )

Change subject: soc/intel/elkhartlake: Lock PAM registers in finalize
......................................................................

soc/intel/elkhartlake: Lock PAM registers in finalize

Use the support from the previous patch to have coreboot lock the PAM
registers instead of the FSP when the lockdown configuration is set to
coreboot.

Change-Id: Ib6fce70d6b0386906850884880dadbf45597452d
Signed-off-by: Tim Wawrzynczak 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57185
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
---
M src/soc/intel/elkhartlake/finalize.c
M src/soc/intel/elkhartlake/fsp_params.c
2 files changed, 11 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c
index 5c36721..3d1430f 100644
--- a/src/soc/intel/elkhartlake/finalize.c
+++ b/src/soc/intel/elkhartlake/finalize.c
@@ -9,8 +9,10 @@
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/pcr.h>
 #include <intelblocks/pmclib.h>
+#include <intelblocks/systemagent.h>
 #include <intelblocks/tco.h>
 #include <intelblocks/thermal.h>
+#include <intelpch/lockdown.h>
 #include <soc/p2sb.h>
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>
@@ -47,12 +49,19 @@
    pmc_clear_pmcon_sts();
 }

+static void sa_finalize(void)
+{
+	if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT)
+		sa_lock_pam();
+}
+
 static void soc_finalize(void *unused)
 {
    printk(BIOS_DEBUG, "Finalizing chipset.\n");

pch_finalize();
    apm_control(APM_CNT_FINALIZE);
+	sa_finalize();

/* Indicate finalize step with post code */
    post_code(POST_OS_BOOT);
diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c
index ae9584c..2bf4a51 100644
--- a/src/soc/intel/elkhartlake/fsp_params.c
+++ b/src/soc/intel/elkhartlake/fsp_params.c
@@ -148,6 +148,7 @@
    	params->PchWriteProtectionEnable[0] = 0;
    	params->PchUnlockGpioPads = 1;
    	params->RtcMemoryLock = 0;
+		params->SkipPamLock = 1;
    } else {
    	params->PchLockDownGlobalSmi = 1;
    	params->PchLockDownBiosLock = 1;
@@ -155,6 +156,7 @@
    	params->PchWriteProtectionEnable[0] = 1;
    	params->PchUnlockGpioPads = 0;
    	params->RtcMemoryLock = 1;
+		params->SkipPamLock = 0;
    }

/* Disable PAVP */