[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Fix TSC frequency calculation

[Nikolai Vyssotski (Code Review)]

Nikolai Vyssotski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45055 )

Change subject: soc/amd/picasso: Fix TSC frequency calculation
......................................................................

soc/amd/picasso: Fix TSC frequency calculation

Fix TSC frequency calculation per Picasso PPR. This code was copied
from Stoney and was incorrect for Picasso.

BUG=b:163423984
TEST=verify Dalboz TSC to be 1GHz
BRANCH=zork

Change-Id: Ibe3f49c7d295e7336ee042da2b94823171b6eb55
Signed-off-by: Nikolai Vyssotski 
---
M src/soc/amd/picasso/tsc_freq.c
1 file changed, 11 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/45055/1

diff --git a/src/soc/amd/picasso/tsc_freq.c b/src/soc/amd/picasso/tsc_freq.c
index a86080c..c863657 100644
--- a/src/soc/amd/picasso/tsc_freq.c
+++ b/src/soc/amd/picasso/tsc_freq.c
@@ -22,9 +22,17 @@
    if (!(msr.hi & 0x80000000))
    	die("Unknown error: cannot determine P-state 0\n");

-	cpufid = (msr.lo & 0x3f);
-	cpudid = (msr.lo & 0x1c0) >> 6;
+	cpufid = (msr.lo & 0xff);
+	cpudid = (msr.lo & 0x3f00) >> 8;

-	mhz = (100 * (cpufid + 0x10)) / (0x01 << cpudid);
+	if (!cpudid)
+		mhz = 0;
+	else if ((cpudid >= 8) && (cpudid < 0x3c))
+		mhz = (unsigned long) ((200 * cpufid) / cpudid);
+	else {
+		printk(BIOS_INFO, "Incorrect core frequency divisor %x, assume 1\n", cpudid);
+		mhz = (unsigned long) (25 * cpufid);
+	}
+
    return mhz;
 }