[coreboot-gerrit] Change in coreboot[master]: nb/intel/*: Fill in SMBIOS type 16 on SNB/HSW

[Patrick Rudolph (Code Review)]

Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/43971

to look at the new patch set (#2).

Change subject: nb/intel/*: Fill in SMBIOS type 16 on SNB/HSW
......................................................................

nb/intel/*: Fill in SMBIOS type 16 on SNB/HSW

Fill in the maximum DRAM capacity and slot count read from CAPID0_A
registers on Sandy Bridge and Haswell.

While the register isn't part of the Core Series datasheet, it can be
found in the corresponding "Intel Open Source Graphics Programmer's
Reference" datasheets.

Change-Id: I6e2346de1ffe52e8685276acbdbf25755f4cc162
Signed-off-by: Patrick Rudolph 
---
M src/northbridge/intel/haswell/hostbridge_regs.h
M src/northbridge/intel/haswell/raminit.c
M src/northbridge/intel/sandybridge/hostbridge_regs.h
M src/northbridge/intel/sandybridge/raminit.c
4 files changed, 96 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/43971/2