[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Reorganize memory initialization support

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39865 )

Change subject: soc/intel/tigerlake: Reorganize memory initialization support
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Patch Set 7:

Hey guys, Uploaded another round of changes since I was looking at the follow-up DDR4 CL and the EDS and there are some differences w.r.t. # of channels and how DQ/DQS mapping is done for DDR4. Also, the way FSP UPDs are organized is really odd -- what UPD calls out as separate channel # for DQ/DQS might not really be a channel from a memory interface standpoint(at least for DDR4 -- looks like the UPDs for LPDDR4x are just overloaded for use by DDR4). Let me know what you think about this patchset.