Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37492
to look at the new patch set (#5).
Change subject: soc/amd/picasso: Cache ramstage load area ......................................................................
soc/amd/picasso: Cache ramstage load area
Set a variable MTRR to WB for the region where ramstage will be loaded. A subsequent change will also cache TSEG once picasso accurately reports the region.
Change-Id: I0a31802052ac7b20871f41c80d0416ee09f8f87c Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com --- M src/soc/amd/picasso/romstage.c 1 file changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/37492/5