Marshall Dawson uploaded patch set #5 to this change.

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soc/amd/picasso: Cache ramstage load area

Set a variable MTRR to WB for the region where ramstage will be loaded.
A subsequent change will also cache TSEG once picasso accurately reports
the region.

Change-Id: I0a31802052ac7b20871f41c80d0416ee09f8f87c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
---
M src/soc/amd/picasso/romstage.c
1 file changed, 22 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/37492/5

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