[coreboot-gerrit] [S] Change in coreboot[main]: util/cbfstool: Place XIP components and FIT at high flash addresses

[Patrick Rudolph (Code Review)]

Attention is currently required from: Andrey Petrov, Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Julius Werner, Ronak Kanabar, Shuo Liu, Tim Chu, Yu-Ping Wu.

Patrick Rudolph has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/86570?usp=email )

Change subject: util/cbfstool: Place XIP components and FIT at high flash addresses
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Patch Set 8:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/86570/comment/08c1a767_1623f0f2?usp... :
PS8, Line 9: CACHE_ROM_SIZE
> The problem is that - the cached region cannot be arbitrarily grown due to limitation of early SoC c […]

I don't get the problem. Of course it can be grown arbitrarily.
If you don't access the whole SPI, but only a small region (like a CBFS file), it will use the same amount in the cache as it would when the file is located in the upper part. If there's not enough cache it will evict cache lines, no matter where it's positioned in flash.

I don't see the correlation to cache as ram.