[coreboot-gerrit] Change in coreboot[master]: sb/intel/i82801gx: Use PCI bitwise ops

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42191 )

Change subject: sb/intel/i82801gx: Use PCI bitwise ops
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Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/42191/2/src/southbridge/intel/i8280... 
File src/southbridge/intel/i82801gx/azalia.c:

https://review.coreboot.org/c/coreboot/+/42191/2/src/southbridge/intel/i8280... 
PS2, Line 201: ~0x00ff0000
> We usually negate and-masks when doing RMW (Read Modify Write) ops. […]

it will give '0xFFFFFFFFFF00FFFF' :)

I'm somehow confused by the negation :p I would keep it '0xff00ffff'.