Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42191 )
Change subject: sb/intel/i82801gx: Use PCI bitwise ops ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42191/2/src/southbridge/intel/i8280... File src/southbridge/intel/i82801gx/azalia.c:
https://review.coreboot.org/c/coreboot/+/42191/2/src/southbridge/intel/i8280... PS2, Line 201: ~0x00ff0000
This is 32-bit code, and the negation implicitly promotes to int only, which is 32-bit. […]
Used ~(0xff << 16)
https://review.coreboot.org/c/coreboot/+/42191/2/src/southbridge/intel/i8280... File src/southbridge/intel/i82801gx/pcie.c:
https://review.coreboot.org/c/coreboot/+/42191/2/src/southbridge/intel/i8280... PS2, Line 52: 0x0c
Because I copypasted the code from another southbridge. Will fix.
Done