Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Paul Menzel,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40242
to look at the new patch set (#8).
Change subject: mb/google/volteer: fix incorrect fields in SPDs ......................................................................
mb/google/volteer: fix incorrect fields in SPDs
According to Intel Document #616599, 1) SPD byte offset #5 for Tiger Lake should be "0x21" (16 rows, 10 columns) 2) SPD byte offset #13 for Tiger Lake should be "0x01" (1 channel x16)
This change fixes those two values in the existing SPD files for Volteer, and zero's byte 9 (bytes 8-11 should be zero'd out in a generic SPD).
BUG=b:152827558 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot Volteer to kernel.
Change-Id: Ice6a32a2b3827cf99d8e109731ffd9efabf68de1 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex M src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex 2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/40242/8