Martin Roth (gaumless@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8064
-gerrit
commit bd2d4b884c4958e75104727e92473f5cf91c50b9 Author: Martin Roth martin.roth@se-eng.com Date: Fri Jan 2 19:02:44 2015 -0700
FSP chipsets: Use macro for 32 & 64 bit signatures
This takes what was already being done for the MRC_DATA_SIGNATURE and turns it into a macro, then uses that macro in all of the other places a 32-bit signature is needed. The macro is extended to 64-bits to use for all of the 64-bit signatures.
This just makes things easier to read and understand.
Change-Id: Ie5579056dbc4d10650ed77f91d5351615d394644 Signed-off-by: Martin Roth martin.roth@se-eng.com --- src/drivers/intel/fsp/fsp_util.c | 5 ++--- src/drivers/intel/fsp/fsp_util.h | 8 ++++++-- src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h | 3 +-- src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.h | 6 ++---- src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h | 3 +-- 5 files changed, 12 insertions(+), 13 deletions(-)
diff --git a/src/drivers/intel/fsp/fsp_util.c b/src/drivers/intel/fsp/fsp_util.c index 3e3f727..8a059ac 100644 --- a/src/drivers/intel/fsp/fsp_util.c +++ b/src/drivers/intel/fsp/fsp_util.c @@ -126,7 +126,7 @@ volatile u8 * find_fsp () fsp_ptr = (u8 *) CONFIG_FSP_LOC;
/* Check the FV signature, _FVH */ - if (((EFI_FIRMWARE_VOLUME_HEADER *)fsp_ptr)->Signature == 0x4856465F) { + if (((EFI_FIRMWARE_VOLUME_HEADER *)fsp_ptr)->Signature == FIRMWARE_VOLUME_SIGNATURE) { /* Go to the end of the FV header and align the address. */ fsp_ptr += ((EFI_FIRMWARE_VOLUME_HEADER *)fsp_ptr)->ExtHeaderOffset; fsp_ptr += ((EFI_FIRMWARE_VOLUME_EXT_HEADER *)fsp_ptr)->ExtHeaderSize; @@ -169,8 +169,7 @@ volatile u8 * find_fsp ()
/* Verify the FSP ID */ if (((u32)fsp_ptr > 0xff) && - ((*(u32 *)(fsp_ptr + FSP_IMAGE_ID_LOC) != FSP_IMAGE_ID_DWORD0) || - (*(u32 *)(fsp_ptr + (FSP_IMAGE_ID_LOC + 4)) != FSP_IMAGE_ID_DWORD1))) { + (*(u64 *)(fsp_ptr + FSP_IMAGE_ID_LOC) != FSP_IMAGE_ID)) { fsp_ptr = (u8 *)ERROR_FSP_SIG_MISMATCH; }
diff --git a/src/drivers/intel/fsp/fsp_util.h b/src/drivers/intel/fsp/fsp_util.h index 64a5e7f..82723eb 100644 --- a/src/drivers/intel/fsp/fsp_util.h +++ b/src/drivers/intel/fsp/fsp_util.h @@ -20,6 +20,9 @@ #ifndef FSP_UTIL_H #define FSP_UTIL_H
+#define SIG_32_BIT(a,b,c,d) ((a<<0)|(b<<8)|(c<<16)|(d<<24)) +#define SIG_64_BIT(a,b,c,d,e,f,g,h) ((a<<0)|(b<<8)|(c<<16)|(d<<24)|((u64)e<<32)|((u64)f<<40)|((u64)g<<48)|((u64)h<<56)) + #include <chipset_fsp_util.h> #include "fsp_values.h"
@@ -57,7 +60,7 @@ void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr);
#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) #define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) +#define MRC_DATA_SIGNATURE SIG_32_BIT('M','R','C','D')
struct mrc_data_container { u32 mrc_signature; // "MRCD" @@ -80,7 +83,8 @@ void update_mrc_cache(void *unused); #define FSP_IMAGE_ID_LOC 16 #define FSP_IMAGE_BASE_LOC 28
-#define FSP_SIG 0x48505346 /* 'FSPH' */ +#define FSP_SIG SIG_32_BIT('F','S','P','H') +#define FIRMWARE_VOLUME_SIGNATURE SIG_32_BIT('_','F','V','H')
#define ERROR_NO_FV_SIG 1 #define ERROR_NO_FFS_GUID 2 diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h index 3057865..7e07c9a 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h @@ -46,7 +46,6 @@ * can be used to verify that the right FSP binary is loaded. * For the Rangeley FSP, the Image Id is "AVN-FSP0". */ -#define FSP_IMAGE_ID_DWORD0 0x2d4e5641 /* 'AVN-' */ -#define FSP_IMAGE_ID_DWORD1 0x30505346 /* 'FSP0' */ +#define FSP_IMAGE_ID SIG_64_BIT('A','V','N','-','F','S','P','0')
#endif /* CHIPSET_FSP_UTIL_H */ diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.h b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.h index f05b0fc..0018313 100644 --- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.h +++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.h @@ -52,12 +52,10 @@
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX) /* ST2-FSP0 */ -#define FSP_IMAGE_ID_DWORD0 0x2D325453 -#define FSP_IMAGE_ID_DWORD1 0x30505346 +#define FSP_IMAGE_ID SIG_64_BIT('S','T','2','-','F','S','P','0') #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X) /* CC2-FSP\0 */ -#define FSP_IMAGE_ID_DWORD0 0x2D324343 -#define FSP_IMAGE_ID_DWORD1 0x00505346 +#define FSP_IMAGE_ID SIG_64_BIT('C','C','2','-','F','S','P',0) #endif
#ifdef __PRE_RAM__ diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h index 1f4fa74..bf73fc4 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h @@ -44,8 +44,7 @@ * can be used to verify that the right FSP binary is loaded. * For the Bay Trail FSP, the Image Id is "VLYVIEW0". */ -#define FSP_IMAGE_ID_DWORD0 0x56594C56 /* 'VLYV' */ -#define FSP_IMAGE_ID_DWORD1 0x30574549 /* 'IEW0' */ +#define FSP_IMAGE_ID SIG_64_BIT('V','L','Y','V','I','E','W','0')
/* Revision of the FSP binary */ #define FSP_GOLD3_REV_ID 0x00000303