[coreboot-gerrit] Change in coreboot[master]: AGESA, binaryPI: implement C bootblock

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36914 )

Change subject: AGESA, binaryPI: implement C bootblock
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Patch Set 31:
> Patch Set 31:
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> IIRC you've also been doing work to begin relying on soc/amd/common.  Did you give any thought to using common/block/car and remove the cache_as_ram.S file here?  Also, it seems like we have these DCACHE_* symbols duplicated in many places.  I wonder whether they could be consolidated into block/car/Kconfig.

I decided against attempts for a common cache_as_ram.S after three months of silence on CB:34883 from AMD and Silverback in fixing their/your design. Nor do we have access to the documentation or the source of CAR teardown changes that were made for amd/stoneyridge and we are also stuck with the old binaryPI blobs.