Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config
......................................................................
Patch Set 61:
(2 comments)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/15210966_fb22d95e
PS60, Line 142: PCIE_CLK_FREE
Looks like PCIE_CLK_FREE got reused for two different purposes. […]
Done
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/50eb79f9_dbd9d35a
PS60, Line 33: PCIE_CLK_FREE
Oh, I think we should deal with LAN 0x70 as well?
Done
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