[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Introduce enums for SPI read mode and speed

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/40823 )

Change subject: soc/amd/picasso: Introduce enums for SPI read mode and speed
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soc/amd/picasso: Introduce enums for SPI read mode and speed

This change adds enums for spi_read_mode and spi100_speed in
preparation for adding these to chip.h in follow-up CLs. This makes it
easier to reference what the mainboard is expected to set for these
SPI configs.

BUG=b:147758054,b:153675510
BRANCH=trembyle-bringup
TEST=Verified that SPI configuration is correct for trembyle.

Signed-off-by: Furquan Shaikh 
Change-Id: I7f9778b41bd059a50f20993415ebd8702a1ad58e
---
M src/soc/amd/picasso/include/soc/southbridge.h
M src/soc/amd/picasso/southbridge.c
2 files changed, 41 insertions(+), 26 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/40823/2