Attention is currently required from: Christian Walter, Elyes Haouas, Martin L Roth, Maximilian Brune, Philipp Hug, ron minnich.
Carlos López has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/85729?usp=email )
Change subject: Upgrade GCC to 15-20241215 Snapshot
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Patch Set 11:
(1 comment)
Patchset:
PS11:
May I ask why is RISC-V support is being removed? I see maintainers assigned to most of the files deleted by this change. Also, the code works - I have not tried the SiFive boards, but I've booted OpenSBI + Linux + u-root on qemu.
I have opened several changes to enable vboot on RISC-V (see https://review.coreboot.org/c/coreboot/+/85677), and a colleague of mine has also sent a fix for Spike (https://review.coreboot.org/c/coreboot/+/85800).
We are considering using coreboot for a novel RISC-V product, it would be sad to see support just disappear.
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