Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40335 )
Change subject: src/arch/x86/acpi: Increase Max PCI bus count support ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/40335/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40335/1//COMMIT_MSG@10 PS1, Line 10: SoC specification [Ice Lake EDS vol 1 chapter 3.18]
ICL can address multiple PCI segments, but does it really have them?
As per EDS, the formula out there
https://review.coreboot.org/c/coreboot/+/40335/1//COMMIT_MSG@10 PS1, Line 10: 1
vol 2?
Ack
https://review.coreboot.org/c/coreboot/+/40335/1/src/arch/x86/acpi.c File src/arch/x86/acpi.c:
https://review.coreboot.org/c/coreboot/+/40335/1/src/arch/x86/acpi.c@114 PS1, Line 114: end_bus_number
This is `u8` too and we can't change it. Having more than 256 buses means […]
got your point, we can have a wrapper here which converts (end / 256) into end_bus_number and (end % 256) into pci_segment_group_number ?