[coreboot-gerrit] Change in ...coreboot[master]: sb/intel/i82801ix: Select SOUTHBRIDGE_INTEL_COMMON_SPI

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33064 )

Change subject: sb/intel/i82801ix: Select SOUTHBRIDGE_INTEL_COMMON_SPI
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Patch Set 1:

Actually with TSC_MONOTONIC_TIMER selected you get:

ICH SPI: Data transaction error
SF: Failed to send command 9f: 1
flash size 0x80000 bytes
SF: Detected Opaque HW-sequencing with sector size 0x100, total 0x80000
SF size 0x80000 does not correspond to CONFIG_ROM_SIZE 0x200000!!

Maybe a better Kconfig like BOOT_DEVICE_NOT_SPI_FLASH could be used here?
I think that also makes sense for some ich7 boards that feature LPC flash.