Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47724 )
Change subject: mb/google/hatch: add non-ChromeOS FMAPs ......................................................................
mb/google/hatch: add non-ChromeOS FMAPs
Add 16MiB/32MiB FMAPs for both hatch and puff baseboard-based boards
Change-Id: I296ef6ed5b46655b7d283105acdc201b6293bbd1 Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/mainboard/google/hatch/Kconfig A src/mainboard/google/hatch/default-hatch-16MiB.fmd A src/mainboard/google/hatch/default-hatch-32MiB.fmd A src/mainboard/google/hatch/default-puff-16MiB.fmd A src/mainboard/google/hatch/default-puff-32MiB.fmd 5 files changed, 84 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/47724/1
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 12e5638..6df8fc4 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -96,15 +96,19 @@ if BOARD_GOOGLE_BASEBOARD_HATCH config FMDFILE string - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-hatch-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-hatch-32MiB.fmd" if BOARD_ROMSIZE_KB_32768 + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-hatch-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 && CHROMEOS + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-hatch-32MiB.fmd" if BOARD_ROMSIZE_KB_32768 && CHROMEOS + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/default-hatch-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/default-hatch-32MiB.fmd" if BOARD_ROMSIZE_KB_32768 endif
if BOARD_GOOGLE_BASEBOARD_PUFF config FMDFILE string - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-puff-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-puff-32MiB.fmd" if BOARD_ROMSIZE_KB_32768 + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-puff-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 && CHROMEOS + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-puff-32MiB.fmd" if BOARD_ROMSIZE_KB_32768 && CHROMEOS + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/default-puff-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/default-puff-32MiB.fmd" if BOARD_ROMSIZE_KB_32768
config POWER_OFF_ON_CR50_UPDATE bool diff --git a/src/mainboard/google/hatch/default-hatch-16MiB.fmd b/src/mainboard/google/hatch/default-hatch-16MiB.fmd new file mode 100644 index 0000000..d07d922 --- /dev/null +++ b/src/mainboard/google/hatch/default-hatch-16MiB.fmd @@ -0,0 +1,17 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL@0x0 0x400000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x3ff000 + } + SI_BIOS@0x400000 0xc00000 { + # SMMSTORE requires 64k alignment + SMMSTORE 0x40000 + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + FMAP 0x800 + RO_VPD 0x4000 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/google/hatch/default-hatch-32MiB.fmd b/src/mainboard/google/hatch/default-hatch-32MiB.fmd new file mode 100644 index 0000000..d7455cf --- /dev/null +++ b/src/mainboard/google/hatch/default-hatch-32MiB.fmd @@ -0,0 +1,20 @@ +FLASH@0xff000000 0x2000000 { + SI_ALL@0x0 0x400000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x3ff000 + } + # Place the start of BIOS region such that it aligns with + # the start of the 16MiB boundary. Since this is a 32MiB + # SPI flash only the top 16MiB actually gets memory mapped. + SI_BIOS@0x1000000 0x1000000 { + # SMMSTORE requires 64k alignment + SMMSTORE 0x40000 + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + FMAP 0x800 + RO_VPD 0x4000 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/google/hatch/default-puff-16MiB.fmd b/src/mainboard/google/hatch/default-puff-16MiB.fmd new file mode 100644 index 0000000..591b469 --- /dev/null +++ b/src/mainboard/google/hatch/default-puff-16MiB.fmd @@ -0,0 +1,18 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL@0x0 0x300000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x2ff000 + } + SI_BIOS@0x300000 0xd00000 { + # SMMSTORE requires 64k alignment + SMMSTORE 0x40000 + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + FMAP 0x800 + RO_VPD 0x4000 + RW_SPD_CACHE(PRESERVE) 0x1000 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/google/hatch/default-puff-32MiB.fmd b/src/mainboard/google/hatch/default-puff-32MiB.fmd new file mode 100644 index 0000000..bdb9baf --- /dev/null +++ b/src/mainboard/google/hatch/default-puff-32MiB.fmd @@ -0,0 +1,21 @@ +FLASH@0xff000000 0x2000000 { + SI_ALL@0x0 0x300000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x2ff000 + } + # Place the start of BIOS region such that it aligns with + # the start of the 16MiB boundary. Since this is a 32MiB + # SPI flash only the top 16MiB actually gets memory mapped. + SI_BIOS@0x1000000 0x1000000 { + # SMMSTORE requires 64k alignment + SMMSTORE 0x40000 + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + FMAP 0x800 + RO_VPD 0x4000 + RW_SPD_CACHE(PRESERVE) 0x1000 + COREBOOT(CBFS) + } +}