[coreboot-gerrit] Change in coreboot[master]: coreboot_tables: Add PCIe info to coreboot table

[Yu-Ping Wu (Code Review)]

Attention is currently required from: Shelley Chen, Ravi Kumar Bokka, Hung-Te Lin, Nico Huber, Tim Wawrzynczak, Paul Menzel, Rex-BC Chen, Julius Werner, Arthur Heymans, Jianjun Wang.
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 )

Change subject: coreboot_tables: Add PCIe info to coreboot table
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Patch Set 20:

(1 comment)

Patchset:

PS9:
> > I really don't understand where the 1MB number is coming from here. […]

From Qualcomm's reply, 1MB is max possible PCIe endpoints. Therefore, for now there seems to be no need to store `mmio_size` (and `config_offset` and `atu_offset`) in the coreboot table.

However, apparently some people understand PCIe better than I do. Tim/Nico, if you still have questions regarding the 1MB MMIO size, could you start a new thread in either CB:61773 or CB:57615? Here doesn't seem to be the best place to discuss that, because qualcomm never showed up. Once we get our questions clarified, we may resume the discussion about the coreboot table structure here. Thanks.