Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38494 )
Change subject: drivers/net/r8168: Add SSDT Power Resource Methods ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38494/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38494/5//COMMIT_MSG@9 PS5, Line 9: Turns out when going into S0ix we want the kernel to toggle de-assert to 0 for : the ISOLATE# pin on the NIC for S0ix not to be woken by PCIe traffic on PCH.
Does this still allow wake from ethernet to work?
Although WoL still doesn't work the Realtek datasheet says that the wake pin is explicitly not affected by this. The intent is for the wake and isolate to be used in tandem.
https://review.coreboot.org/c/coreboot/+/38494/5/src/arch/x86/acpi_device.c File src/arch/x86/acpi_device.c:
PS5:
Can you please push this change as a separate CL?
Done
https://review.coreboot.org/c/coreboot/+/38494/5/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/overridetree.cb:
PS5:
Can you please push the mainboard change as a separate CL?
Done