[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Add enable PCH FIVR entry

[Sumeet R Pawnikar (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph.
Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58140 )

Change subject: soc/intel/alderlake: Add enable PCH FIVR entry
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soc/intel/alderlake: Add enable PCH FIVR entry

Add PCH FIVR enable entry for AlderLake based mainboard configuration.

Change-Id: I570ef5a741fa96efaee0457815f4ef9808edb10d
Signed-off-by: Sumeet Pawnikar 
---
M src/soc/intel/alderlake/acpi.c
M src/soc/intel/alderlake/chip.h
2 files changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/58140/1

diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c
index b28ec12..28739a1 100644
--- a/src/soc/intel/alderlake/acpi.c
+++ b/src/soc/intel/alderlake/acpi.c
@@ -272,6 +272,9 @@
    /* Enable DPTF based on mainboard configuration */
    gnvs->dpte = config->dptf_enable;

+	/* Enable PCH FIVR based on mainboard configuration */
+	gnvs->pche = config->pch_fivr_enable;
+
    /* Set USB2/USB3 wake enable bitmaps. */
    gnvs->u2we = config->usb2_wake_enable_bitmap;
    gnvs->u3we = config->usb3_wake_enable_bitmap;
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 270400b..412cdf5 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -163,6 +163,8 @@
    uint8_t TcssD3ColdDisable;
    /* Enable DPTF support */
    int dptf_enable;
+	/* Enable PCH FIVR support */
+	int pch_fivr_enable;

/* Deep SX enable for both AC and DC */
    int deep_s3_enable_ac;