Attention is currently required from: Tim Wawrzynczak, Subrata Banik, Angel Pons, Patrick Rudolph, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50162 )
Change subject: soc/intel/alderlake: Add support for external clock buffer ......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50162/comment/6a1016f8_a802a8e2 PS1, Line 9: 3 CLKSRC using external clock buffer. : CLKSRC 6 provides feed clock to discrete buffer for further : distribution to platform. This is mainboard specific design and nothing to do with what SoC supports.
From SoC standpoint, it supports 7 CLKSRC signals. How those signals are routed on the board is mainboard design.
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/50162/comment/87456af5_0dddfb07 PS1, Line 152: GEN3_EXTERNAL_CLOCK_BUFFER I don't understand why this is a SoC config. It is a mainboard-specific design.
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/50162/comment/5b835319_54437f31 PS1, Line 156: m_cfg->PcieClkSrcUsage[i] = 0;
Did you send me the schematics?
Subrata, I do not understand what this change is trying to achieve.
There are 7 CLKSRCs on ADL-P. Thus, FSP UPDs need to know how each of these CLKSRCs are routed -- RP, Free running, LAN, etc.
Beyond that, a mainboard might choose to distribute any clock source in any way it wants. But, FSP doesn't really care about that because there is nothing in the SoC that needs to be configured for the additional clock sources that are generated by the mainboard.
So, why is this code setting PcieClkSrcUsage for something that the FSP doesn't care about?