Hello build bot (Jenkins), Furquan Shaikh, Lee Leahy, Julius Werner, Angel Pons, Huang Jin, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46855
to look at the new patch set (#10).
Change subject: mrc_cache: Move code for triggering memory training into mrc_cache ......................................................................
mrc_cache: Move code for triggering memory training into mrc_cache
Currently the decision of whether or not to use mrc_cache in recovery mode is made within the individual platforms' drivers (ie: fsp2.0, fsp1.1, etc.). As this is not platform specific, but uses common vboot infrastructure, the code can be unified and moved into mrc_cache. The conditions are as follows:
1. If HAS_RECOVERY_MRC_CACHE, use mrc_cache data (unless retrain switch is true) 2. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_BOOTBLOCK, this means that memory training will occur after verified boot, meaning that mrc_cache will be filled with data from executing RW code. So in this case, we never want to use the training data in the mrc_cache for recovery mode. 3. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_ROMSTAGE, this means that memory training happens before verfied boot, meaning that the mrc_cache data is generated by RO code, so it is safe to use for a recovery boot. 4. Any platform that does not use vboot should be unaffected.
Additionally, we have removed the MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config because the mrc_cache driver takes care of invalidating the mrc_cache data for normal mode. If the platform: 1. !HAS_RECOVERY_MRC_CACHE, always invalidate mrc_cache data 2. HAS_RECOVERY_MRC_CACHE, only invalidate if retrain switch is set
BUG=b:150502246 BRANCH=None TEST=1. run dut-control power_state:rec_force_mrc twice on lazor ensure that memory retraining happens both times run dut-control power_state:rec twice on lazor ensure that memory retraining happens only first time 2. remove HAS_RECOVERY_MRC_CACHE from lazor Kconfig boot twice to ensure caching of memory training occurred on each boot.
Change-Id: I3875a7b4a4ba3c1aa8a3c1507b3993036a7155fc Signed-off-by: Shelley Chen shchen@google.com --- M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/mrc_cache/Kconfig M src/drivers/mrc_cache/mrc_cache.c M src/mainboard/google/dedede/Kconfig M src/mainboard/google/deltaur/Kconfig M src/mainboard/google/drallion/Kconfig M src/mainboard/google/eve/Kconfig M src/mainboard/google/fizz/Kconfig M src/mainboard/google/hatch/Kconfig M src/mainboard/google/octopus/Kconfig M src/mainboard/google/poppy/Kconfig M src/mainboard/google/reef/Kconfig M src/mainboard/google/sarien/Kconfig M src/mainboard/google/volteer/Kconfig M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/glkrvp/Kconfig M src/mainboard/intel/jasperlake_rvp/Kconfig M src/mainboard/intel/tglrvp/Kconfig M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/qualcomm/sc7180/Kconfig 23 files changed, 104 insertions(+), 105 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/46855/10