[coreboot-gerrit] Change in coreboot[master]: soc/intel/fsp_broadwell_de: Enable SSE and SSE2

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35617 )

Change subject: soc/intel/fsp_broadwell_de: Enable SSE and SSE2
......................................................................

soc/intel/fsp_broadwell_de: Enable SSE and SSE2

Apparently romcc-bootblock just barely built without
XMM registers.

Change-Id: Ie7b1101f47c2dfb718bef99f8c05f9d575c821cd
Signed-off-by: Kyösti Mälkki 
---
M src/soc/intel/fsp_broadwell_de/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/35617/1

diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig
index 9c91d7c..88ad586 100644
--- a/src/soc/intel/fsp_broadwell_de/Kconfig
+++ b/src/soc/intel/fsp_broadwell_de/Kconfig
@@ -18,6 +18,7 @@
    select PARALLEL_MP
    select SMP
    select IOAPIC
+	select SSE2
    select UDELAY_TSC
    select SUPPORT_CPU_UCODE_IN_CBFS
    select INTEL_DESCRIPTOR_MODE_CAPABLE