[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Configure TCSS xHCI and xDCI

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS xHCI and xDCI
......................................................................

soc/intel/tigerlake: Configure TCSS xHCI and xDCI

Configure xHCI, xDCI according to board design

BUG=none
BRANCH=none
TEST=Build and boot to OS

Signed-off-by: Wonkyu Kim 
Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38624
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
2 files changed, 10 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Wonkyu Kim: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 3f980d1..4f57b0e 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2019 Intel Corporation.
+ * Copyright (C) 2019-2020 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -218,6 +218,10 @@
    	FORCE_ENABLE,
    } CnviBtAudioOffload;

+	/* Tcss */
+	uint8_t TcssXhciEn;
+	uint8_t TcssXdciEn;
+
    /*
     * Override GPIO PM configuration:
     * 0: Use FSP default GPIO PM program,
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
index 9c105ca..fc3155f 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2019 Intel Corp.
+ * Copyright (C) 2019-2020 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -105,6 +105,10 @@
    /* Image clock: disable all clocks for bypassing FSP pin mux */
    memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn));

+	/* Tcss */
+	m_cfg->TcssXhciEn = config->TcssXhciEn;
+	m_cfg->TcssXdciEn = config->TcssXdciEn;
+
    /* Enable Hyper Threading */
    m_cfg->HyperThreading = 1;
    /* Disable Lock PCU Thermal Management registers */