[coreboot-gerrit] [S] Change in coreboot[master]: soc/intel/cmn/cse: API to perform essential CSE operations post EOP

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69977 )

(

5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/intel/cmn/cse: API to perform essential CSE operations post EOP
......................................................................

soc/intel/cmn/cse: API to perform essential CSE operations post EOP

This patch creates an API that can perform essential CSE operation
after sending the late EOP command to the CSE and prior booting to OS.

Lists of operation are
- Perform global reset lock
- Put HECI1 to D0i3 and disable the HECI1 if the user selects
- Set D0I3 for all HECI devices.

BUG=b:260041679
TEST=Able to boot Google/Rex after sending CSE EOP late.

Signed-off-by: Subrata Banik 
Change-Id: I10131ea9b553a62f0d632783c4dbad96d35d6563
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69977
Reviewed-by: Kapil Porwal 
Reviewed-by: Lean Sheng Tan 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 47 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Lean Sheng Tan: Looks good to me, approved
  Kapil Porwal: Looks good to me, approved

diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 9b8db54..8f32c7c 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -1256,6 +1256,22 @@
 }

/*
+ * This function to perform essential post EOP cse related operations
+ * upon SoC selecting `SOC_INTEL_CSE_SEND_EOP_LATE` config
+ */
+void cse_late_finalize(void)
+{
+	if (!CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE))
+		return;
+
+	if (!CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT))
+		cse_final_ready_to_boot();
+
+	if (!CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
+		cse_final_end_of_firmware();
+}
+
+/*
  * `cse_final` function is native implementation of equivalent events performed by
  * each FSP NotifyPhase() API invocations.
  */
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index cceee4f..bccdc4e 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -542,6 +542,12 @@
 void cse_send_end_of_post(void);

/*
+ * This function to perform essential post EOP cse related operations
+ * upon SoC selecting `SOC_INTEL_CSE_SEND_EOP_LATE` config
+ */
+void cse_late_finalize(void);
+
+/*
  * SoC override API to make heci1 disable using PCR.
  *
  * Allow SoC to implement heci1 disable override due to PSF registers being