[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8183: Set correct threshold of EMI bandwidth for DVFS ...

[Duan huayang (Code Review)]

Duan huayang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39034 )

Change subject: soc/mediatek/mt8183: Set correct threshold of EMI bandwidth for DVFS switch
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Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39034/4/src/soc/mediatek/mt8183/emi... 
File src/soc/mediatek/mt8183/emi.c:

https://review.coreboot.org/c/coreboot/+/39034/4/src/soc/mediatek/mt8183/emi... 
PS4, Line 305: 0x0a000705
> I checked the datasheet and thought BW_2ND_INT_BW_THR should be set in bits 22:16 instead of the hig […]

the datasheet have mistake here, from the hardware design, BW_2ND_INT_BW_THR should be [30:24], not [22:16], however, the logic of DRAM driver is correct,  only the datasheet offset is wrong.