Duan huayang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39034 )
Change subject: soc/mediatek/mt8183: Set correct threshold of EMI bandwidth for DVFS switch
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39034/4/src/soc/mediatek/mt8183/emi...
File src/soc/mediatek/mt8183/emi.c:
https://review.coreboot.org/c/coreboot/+/39034/4/src/soc/mediatek/mt8183/emi...
PS4, Line 305: 0x0a000705
I checked the datasheet and thought BW_2ND_INT_BW_THR should be set in bits 22:16 instead of the hig […]
the datasheet have mistake here, from the hardware design, BW_2ND_INT_BW_THR should be [30:24], not [22:16], however, the logic of DRAM driver is correct, only the datasheet offset is wrong.
--
To view, visit
https://review.coreboot.org/c/coreboot/+/39034
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I82c3c70bcd90df3fdd613c0353aba0f176bc82bc
Gerrit-Change-Number: 39034
Gerrit-PatchSet: 4
Gerrit-Owner: huayang duan
huayangduan@gmail.com
Gerrit-Reviewer: Derek Waldner
derek.waldner.os@gmail.com
Gerrit-Reviewer: Duan huayang
huayang.duan@mediatek.com
Gerrit-Reviewer: Hung-Te Lin
hungte@chromium.org
Gerrit-Reviewer: Julius Werner
jwerner@chromium.org
Gerrit-Reviewer: Paul Menzel
paulepanter@users.sourceforge.net
Gerrit-Reviewer: Yu-Ping Wu
yupingso@google.com
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-Reviewer: huayang duan
huayangduan@gmail.com
Gerrit-Comment-Date: Thu, 05 Mar 2020 03:31:40 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Yu-Ping Wu
yupingso@google.com
Gerrit-MessageType: comment