[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Add UPD settings to chip.h

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38699 )

Change subject: soc/amd/picasso: Add UPD settings to chip.h
......................................................................

soc/amd/picasso: Add UPD settings to chip.h

Add values that align with UPD settings.

Signed-off-by: Marshall Dawson 
Change-Id: I6bce44a43e57ba00d2b29cfa6249cef51e9ceabb
---
M src/soc/amd/picasso/chip.h
1 file changed, 41 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/38699/1

diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index 4e9e18b..0681277 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -44,10 +44,51 @@
    	I2S_PINS_I2S_TDM = 4,
    	I2S_PINS_UNCONF = 7,	/* All pads will be input mode */
    } acp_pin_cfg;
+
+	/* Options for these are in src/arch/x86/include/arch/acpi.h */
+	uint8_t  fadt_pm_profile;
+	uint16_t fadt_boot_arch;
+	uint32_t fadt_flags;
+
+	/* System config index */
+	uint8_t system_config;
+
+	/* STAPM Configuration */
+	uint32_t fast_ppt_limit;
+	uint32_t slow_ppt_limit;
+	uint32_t slow_ppt_time_constant;
+	uint32_t stapm_time_constant;
+	uint32_t sustained_power_limit;
+
+	/* PROCHOT_L de-assertion Ramp Time */
+	uint32_t prochot_l_deassertion_ramp_time;
+
+	/* Lower die temperature limit */
+	uint32_t thermctl_limit;
+
+	/* FP5 Processor Voltage Supply PSI Currents. 0 indicates use SOC default */
+	uint32_t psi0_current_limit;
+	uint32_t psi0_soc_current_limit;
+	uint32_t vddcr_soc_voltage_margin;
+	uint32_t vddcr_vdd_voltage_margin;
+
+	/* VRM Limits. 0 indicates use SOC default */
+	uint32_t vrm_maximum_current_limit;
+	uint32_t vrm_soc_maximum_current_limit;
+	uint32_t vrm_current_limit;
+	uint32_t vrm_soc_current_limit;
+
+	/* Misc SMU settings */
+	uint8_t sb_tsi_alert_comparator_mode_en;
+	uint8_t core_dldo_bypass;
+	uint8_t min_soc_vid_offset;
+	uint8_t aclk_dpm0_freq_400MHz;
 };

typedef struct soc_amd_picasso_config config_t;

+const config_t *get_soc_config(void);
+
 extern struct device_operations pci_domain_ops;

#endif /* __PICASSO_CHIP_H__ */