Attention is currently required from: Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Martin Roth, Fred Reitberger, Felix Held.
Robert Zieba has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68139 )
Change subject: soc/amd/mendocino: Enable GPP clk req disabling for disabled devices ......................................................................
soc/amd/mendocino: Enable GPP clk req disabling for disabled devices
This commit enables GPP clk req disabling for disabled PCIe devices. Having clk req enabled when the PCIe device is actually disabled may interfere with the SoC suspending.
BUG=b:250009974 TEST=Ran on skyrim proto device, verified that clk reqs are set appropriately
Change-Id: I6c840f2fa3f9358f58c0386134d23511ff880248 Signed-off-by: Robert Zieba robertzieba@google.com --- M src/mainboard/amd/chausie/Makefile.inc M src/mainboard/google/skyrim/Makefile.inc M src/soc/amd/mendocino/chip.h M src/soc/amd/mendocino/fch.c 4 files changed, 25 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/68139/1
diff --git a/src/mainboard/amd/chausie/Makefile.inc b/src/mainboard/amd/chausie/Makefile.inc index 2560886..98b2cdd 100644 --- a/src/mainboard/amd/chausie/Makefile.inc +++ b/src/mainboard/amd/chausie/Makefile.inc @@ -8,6 +8,7 @@
ramstage-y += chromeos.c ramstage-y += gpio.c +ramstage-y += port_descriptors.c
ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_FT6_Updatable.bin),) APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_FT6_Updatable.bin diff --git a/src/mainboard/google/skyrim/Makefile.inc b/src/mainboard/google/skyrim/Makefile.inc index ba175a2..9eb1e46 100644 --- a/src/mainboard/google/skyrim/Makefile.inc +++ b/src/mainboard/google/skyrim/Makefile.inc @@ -6,6 +6,7 @@
ramstage-y += mainboard.c ramstage-y += ec.c +ramstage-y += port_descriptors.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c
verstage-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += verstage.c diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index 0e656f5..dcd3c70 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -7,6 +7,7 @@
#include <amdblocks/chip.h> #include <amdblocks/i2c.h> +#include <amdblocks/pci_gpp.h> #include <gpio.h> #include <soc/i2c.h> #include <soc/southbridge.h> @@ -92,11 +93,7 @@
/* The array index is the general purpose PCIe clock output number. Values in here aren't the values written to the register to have the default to be always on. */ - enum { - GPP_CLK_ON, /* GPP clock always on; default */ - GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */ - GPP_CLK_OFF, /* GPP clk off */ - } gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE]; + enum gpp_clk_req gpp_clk_config[GPP_CLK_OUTPUT_COUNT];
/* performance policy for the PCIe links: power consumption vs. link speed */ enum { diff --git a/src/soc/amd/mendocino/fch.c b/src/soc/amd/mendocino/fch.c index e86cd31..a04cd1b 100644 --- a/src/soc/amd/mendocino/fch.c +++ b/src/soc/amd/mendocino/fch.c @@ -6,6 +6,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/amd_pci_util.h> #include <amdblocks/gpio.h> +#include <amdblocks/pci_gpp.h> #include <amdblocks/smi.h> #include <assert.h> #include <bootstate.h> @@ -130,7 +131,7 @@ /* configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { - const struct soc_amd_mendocino_config *cfg = config_of_soc(); + struct soc_amd_mendocino_config *cfg = config_of_soc();
/* look-up table to be able to iterate over the PCIe clock output settings */ const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = { @@ -145,6 +146,7 @@
uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL);
+ pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], GPP_CLK_OUTPUT_COUNT); for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) { gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]); /*