Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40002 )
Change subject: mb/google/cyan: Switch eMMC and SD from ACPI to PCI mode ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/40002/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40002/1//COMMIT_MSG@10 PS1, Line 10: SeaBIOS requires : an onerous workaround
Do you have a reference for that?
https://www.seabios.org/Runtime_config#Other_Configuration_items, sdcard entry. Basically, for each eMMC or SD device, you have to create an etc/sdcard entry in the cbfs which contains the PCI BAR0 address for the controller, so that SeaBIOS can init it. There's also no way to generate this at compile time since BAR0 isn't known ahead of time.
https://review.coreboot.org/c/coreboot/+/40002/1//COMMIT_MSG@13 PS1, Line 13: from ACPI mode to PCI mode.
Re-flow for 72/75 characters?
Done
https://review.coreboot.org/c/coreboot/+/40002/1//COMMIT_MSG@14 PS1, Line 14:
Any idea, what the reasoning for ACPI mode was from Chromium OS? Will the OS set this up for itself?
in the ChromeOS scenario, depthcharge will init the controllers so they are available to boot the OS. I believe this was just a carry over from Baytrail. All other non-ChromeOS Braswell/Cherry Trail devices have their eMMC/SD controllers in PCI mode, not ACPI.