Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/28608 )
Change subject: amd/stoneyridge: Sync PSP base to MSR ......................................................................
Patch Set 1:
(1 comment)
It may be worth another try to ask AMD why they think the GPF occurs.
https://review.coreboot.org/#/c/28608/1/src/soc/amd/stoneyridge/cpu.c File src/soc/amd/stoneyridge/cpu.c:
https://review.coreboot.org/#/c/28608/1/src/soc/amd/stoneyridge/cpu.c@123 PS1, Line 123: setup_lapic();
I did a small modification based on your code, and tested. […]
It'd be nice to comment properly what's really needed. Did you check whether the value survived the S3 cycle?
Maybe there's a lock on the register? Perhaps engaged when we call psp_notify_boot_done(), so I'd probably experiment with jamming the MSR at various times to see whether I can create a GPF.
Seems unlikely that it would be writable only a single time.