[coreboot-gerrit] Change in coreboot[master]: sb/amd/sb700/bootblock.c: Use standard PCI access functions

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62104 )

Change subject: sb/amd/sb700/bootblock.c: Use standard PCI access functions
......................................................................

sb/amd/sb700/bootblock.c: Use standard PCI access functions

Signed-off-by: Michał Żygowski 
Change-Id: I7feef4f419188605e665cdb09e8de0fdb0b4f269
---
M src/southbridge/amd/sb700/bootblock.c
1 file changed, 14 insertions(+), 14 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/62104/1

diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c
index d575207..adc18d3 100644
--- a/src/southbridge/amd/sb700/bootblock.c
+++ b/src/southbridge/amd/sb700/bootblock.c
@@ -45,20 +45,20 @@

dev = PCI_DEV(0, 0x14, 3);

-	reg8 = pci_io_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5);
+	reg8 = pci_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5);
    if (CONFIG(SPI_FLASH))
    	/* Disable decode of variable LPC ROM address ranges 1 and 2. */
    	reg8 &= ~((1 << 3) | (1 << 4));
    else
    	/* Decode variable LPC ROM address ranges 1 and 2. */
    	reg8 |= (1 << 3) | (1 << 4);
-	pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5, reg8);
+	pci_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5, reg8);

/* LPC ROM address range 1: */
    /* Enable LPC ROM range mirroring start at 0x000e(0000). */
-	pci_io_write_config16(dev, 0x68, 0x000e);
+	pci_write_config16(dev, 0x68, 0x000e);
    /* Enable LPC ROM range mirroring end at 0x000f(ffff). */
-	pci_io_write_config16(dev, 0x6a, 0x000f);
+	pci_write_config16(dev, 0x6a, 0x000f);

/* LPC ROM address range 2: */
    /*
@@ -69,30 +69,30 @@
     * 0xffc0(0000): 4MB
     * 0xff80(0000): 8MB
     */
-	pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
+	pci_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
    /* Enable LPC ROM range end at 0xffff(ffff). */
-	pci_io_write_config16(dev, 0x6e, 0xffff);
+	pci_write_config16(dev, 0x6e, 0xffff);

/* SB700 LPC Bridge 0x48.
     * Turn on all LPC IO Port decode enables
     */
-	pci_io_write_config32(dev, 0x44, 0xffffffff);
+	pci_write_config32(dev, 0x44, 0xffffffff);

/* SB700 LPC Bridge 0x48.
     * BIT0: Port Enable for SuperIO 0x2E-0x2F
     * BIT1: Port Enable for SuperIO 0x4E-0x4F
     * BIT6: Port Enable for RTC IO 0x70-0x73
     */
-	reg8 = pci_io_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5);
+	reg8 = pci_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5);
    reg8 |= (1 << 0) | (1 << 1) | (1 << 6);
-	pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5, reg8);
+	pci_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5, reg8);

/* SB700 LPC Bridge 0x4a.
     * BIT5: Port Enable for Port 0x80
     */
-	reg8 = pci_io_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6);
+	reg8 = pci_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6);
    reg8 |= (1 << 5);
-	pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6, reg8);
+	pci_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6, reg8);
 }

static void sb700_configure_rom(void)
@@ -107,11 +107,11 @@
    	volatile uint32_t *spi_mmio;

/* Temporarily set up SPI access to change SPI speed */
-		prev_spi_cfg = dword = pci_io_read_config32(dev, SPI_BASE_ADDRESS);
+		prev_spi_cfg = dword = pci_read_config32(dev, SPI_BASE_ADDRESS);
    	dword &= ~0xffffffe0;		/* SPI_BaseAddr */
    	dword |= TEMPORARY_SPI_BASE_ADDRESS;
    	dword |= BIT(1);		/* SpiRomEnable = 1 */
-		pci_io_write_config32(dev, SPI_BASE_ADDRESS, dword);
+		pci_write_config32(dev, SPI_BASE_ADDRESS, dword);

dword = read32(TEMPORARY_SPI_BASE_ADDRESS + SPI_CONTROL_1);
    	dword &= ~(0x3 << 12);	/* NormSpeed = 0x1 */
@@ -119,7 +119,7 @@
    	write32(TEMPORARY_SPI_BASE_ADDRESS + SPI_CONTROL_1, dword);

/* Restore previous SPI access */
-		pci_io_write_config32(dev, SPI_BASE_ADDRESS, prev_spi_cfg);
+		pci_write_config32(dev, SPI_BASE_ADDRESS, prev_spi_cfg);
    }
 }