Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39601 )
Change subject: soc/intel/xeon_sp: Refactor code to allow for additional CPUs ......................................................................
soc/intel/xeon_sp: Refactor code to allow for additional CPUs
Refactor the code and split it into common and CPU-specific code. Move most Skylake-SP code into skx/ and keep common code in the current folder.
This is a preparation for future work that will enable next generation server CPU.
Also, some minor cosmetic clean-ups like include reordering.
Signed-off-by: Andrey Petrov anpetrov@fb.com Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/devicetree.cb M src/mainboard/ocp/tiogapass/dsdt.asl M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/Makefile.inc R src/soc/intel/xeon_sp/bootblock.c M src/soc/intel/xeon_sp/include/soc/iomap.h M src/soc/intel/xeon_sp/include/soc/pcr_ids.h M src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/romstage.c A src/soc/intel/xeon_sp/skx/Kconfig A src/soc/intel/xeon_sp/skx/Makefile.inc R src/soc/intel/xeon_sp/skx/acpi.c R src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl R src/soc/intel/xeon_sp/skx/acpi/iiostack.asl R src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl R src/soc/intel/xeon_sp/skx/acpi/uncore.asl R src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl R src/soc/intel/xeon_sp/skx/chip.c R src/soc/intel/xeon_sp/skx/chip.h R src/soc/intel/xeon_sp/skx/cpu.c R src/soc/intel/xeon_sp/skx/hob_display.c R src/soc/intel/xeon_sp/skx/include/soc/acpi.h R src/soc/intel/xeon_sp/skx/include/soc/cpu.h R src/soc/intel/xeon_sp/skx/include/soc/gpio_soc_defs.h R src/soc/intel/xeon_sp/skx/include/soc/irq.h R src/soc/intel/xeon_sp/skx/include/soc/msr.h R src/soc/intel/xeon_sp/skx/include/soc/nvs.h R src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h R src/soc/intel/xeon_sp/skx/include/soc/pm.h R src/soc/intel/xeon_sp/skx/include/soc/pmc.h R src/soc/intel/xeon_sp/skx/include/soc/ramstage.h R src/soc/intel/xeon_sp/skx/include/soc/soc_util.h R src/soc/intel/xeon_sp/skx/lpc.c A src/soc/intel/xeon_sp/skx/romstage.c R src/soc/intel/xeon_sp/skx/soc_util.c R src/soc/intel/xeon_sp/skx/spi.c R src/soc/intel/xeon_sp/skx/upd_display.c M src/soc/intel/xeon_sp/uncore.c A src/soc/intel/xeon_sp/util.c 41 files changed, 344 insertions(+), 222 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/39601/1
diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index 87e2760..d6b4459 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -21,9 +21,8 @@ def_bool y select BOARD_ROMSIZE_KB_32768 select HAVE_ACPI_TABLES - select SOC_INTEL_XEON_SP select MAINBOARD_USES_FSP2_0 - select FSP_CAR + select SOC_INTEL_SKYLAKE_SP
config MAINBOARD_DIR string diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index 46311d9..902ea80 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -15,7 +15,7 @@ ## GNU General Public License for more details. ##
-chip soc/intel/xeon_sp +chip soc/intel/xeon_sp/skx
register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index aca6c4d..076457e 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -30,12 +30,12 @@ #include "acpi/platform.asl"
// global NVS and variables - #include <soc/intel/xeon_sp/acpi/globalnvs.asl> + #include <soc/intel/xeon_sp/skx/acpi/globalnvs.asl>
#include <cpu/intel/common/acpi/cpu.asl>
// Xeon-SP ACPI tables Scope (_SB) { - #include <soc/intel/xeon_sp/acpi/uncore.asl> + #include <soc/intel/xeon_sp/skx/acpi/uncore.asl> } } diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 94c0ac4..3dcb302 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -1,28 +1,17 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2019 - 2020 Intel Corporation -## Copyright (C) 2019 - 2020 Facebook Inc -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +source "src/soc/intel/xeon_sp/skx/Kconfig"
-config SOC_INTEL_XEON_SP +config XEON_SP_COMMON_BASE bool + +config SOC_INTEL_SKYLAKE_SP + bool + select XEON_SP_COMMON_BASE help - Intel Xeon SP support + Intel Skylake-SP support
-if SOC_INTEL_XEON_SP +if XEON_SP_COMMON_BASE
-config CPU_SPECIFIC_OPTIONS +config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 select ARCH_RAMSTAGE_X86_32 @@ -69,11 +58,6 @@ select POSTCAR_CONSOLE select POSTCAR_STAGE
-config FSP_HEADER_PATH - string "Location of FSP headers" - depends on MAINBOARD_USES_FSP2_0 - default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp" - config MAX_SOCKET int default 2 @@ -90,14 +74,6 @@ help This option allows you to select MMIO Base Address of sideband bus.
-config DCACHE_RAM_BASE - hex - default 0xfe800000 - -config DCACHE_RAM_SIZE - hex - default 0x200000 - config DCACHE_BSP_STACK_SIZE hex default 0x10000 @@ -106,14 +82,6 @@ hex default 0x80000000
-config CPU_MICROCODE_CBFS_LOC - hex - default 0xfff0fdc0 - -config CPU_MICROCODE_CBFS_LEN - hex - default 0x7C00 - config C_ENV_BOOTBLOCK_SIZE hex default 0xC000 @@ -122,5 +90,4 @@ hex default 0x80000
- -endif ## SOC_INTEL_XEON_SP +endif diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 9ad3e77..a48a2f3 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -15,45 +15,15 @@ ## GNU General Public License for more details. ##
-ifeq ($(CONFIG_SOC_INTEL_XEON_SP),y) +ifeq ($(CONFIG_XEON_SP_COMMON_BASE),y)
-subdirs-y += ../../../cpu/intel/microcode -subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/tsc -subdirs-y += ../../../cpu/x86/cache -subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm +subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx
-bootblock-y += bootblock/bootblock.c -bootblock-y += spi.c - -postcar-y += soc_util.c -postcar-y += spi.c - -romstage-y += soc_util.c -romstage-y += reset.c -romstage-y += romstage.c -romstage-y += soc_util.c -romstage-y += spi.c -romstage-y += hob_display.c -romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c -romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c - -ramstage-y += soc_util.c -ramstage-y += uncore.c -ramstage-y += reset.c -ramstage-y += chip.c -ramstage-y += soc_util.c -ramstage-y += lpc.c -ramstage-y += cpu.c -ramstage-y += spi.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c -ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c -ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c -ramstage-y += hob_display.c +bootblock-y += bootblock.c +romstage-y += romstage.c reset.c util.c +ramstage-y += uncore.c reset.c util.c
CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH)
-endif ## CONFIG_SOC_INTEL_XEON_SP +endif ## XEON_SP_COMMON_BASE diff --git a/src/soc/intel/xeon_sp/bootblock/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c similarity index 99% rename from src/soc/intel/xeon_sp/bootblock/bootblock.c rename to src/soc/intel/xeon_sp/bootblock.c index 482f5b5..96f55ac 100644 --- a/src/soc/intel/xeon_sp/bootblock/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -15,11 +15,11 @@ */
#include <bootblock_common.h> +#include <console/console.h> #include <device/pci.h> #include <FsptUpd.h> #include <intelblocks/fast_spi.h> #include <soc/iomap.h> -#include <console/console.h>
const FSPT_UPD temp_ram_init_params = { .FspUpdHeader = { diff --git a/src/soc/intel/xeon_sp/include/soc/iomap.h b/src/soc/intel/xeon_sp/include/soc/iomap.h index 7c825a4..066a2db 100644 --- a/src/soc/intel/xeon_sp/include/soc/iomap.h +++ b/src/soc/intel/xeon_sp/include/soc/iomap.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -30,18 +28,18 @@ #define MAP_ENTRY_LIMIT_32(reg_, mask_bits_, desc_) MAP_ENTRY(reg_, 0, 1, mask_bits_, desc_)
// SPI BAR0 MMIO base address -#define SPI_BASE_ADDRESS 0xfe010000 -#define SPI_BASE_SIZE 0x1000 +#define SPI_BASE_ADDRESS 0xfe010000 +#define SPI_BASE_SIZE 0x1000
-#define ACPI_BASE_ADDRESS 0x500 +#define ACPI_BASE_ADDRESS 0x500
/* Video RAM */ -#define VGA_BASE_ADDRESS 0xa0000 -#define VGA_BASE_SIZE 0x20000 +#define VGA_BASE_ADDRESS 0xa0000 +#define VGA_BASE_SIZE 0x20000
/* High Performance Event Timer */ -#define HPET_BASE_ADDRESS 0xfed00000 +#define HPET_BASE_ADDRESS 0xfed00000
-#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS +#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS
#endif /* _SOC_IOMAP_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/pcr_ids.h b/src/soc/intel/xeon_sp/include/soc/pcr_ids.h index c679692..cf3e737 100644 --- a/src/soc/intel/xeon_sp/include/soc/pcr_ids.h +++ b/src/soc/intel/xeon_sp/include/soc/pcr_ids.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -17,7 +15,7 @@ #ifndef _PCR_IDS_H_ #define _PCR_IDS_H_
-#define PID_ITSS 0xC4 -#define PID_RTC 0xC3 +#define PID_ITSS 0xc4 +#define PID_RTC 0xc3
#endif /* _PCR_IDS_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/romstage.h b/src/soc/intel/xeon_sp/include/soc/romstage.h index 623306f..fa70bcd 100644 --- a/src/soc/intel/xeon_sp/include/soc/romstage.h +++ b/src/soc/intel/xeon_sp/include/soc/romstage.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h new file mode 100644 index 0000000..dc63140 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _XEON_SP_SOC_UTIL_H_ +#define _XEON_SP_SOC_UTIL_H_ + +#include <console/console.h> + +void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3); +void unlock_pam_regions(void); +void get_stack_busnos(uint32_t *bus); + +#define LOG_MEM_RESOURCE(type, dev, index, base_kb, size_kb) \ + printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \ + "end: 0x%llx, size_kb: 0x%llx\n", \ + __func__, __LINE__, type, dev_path(dev), index, (base_kb << 10), \ + (base_kb << 10) + (size_kb << 10) - 1, size_kb) + +#define LOG_IO_RESOURCE(type, dev, index, base, size) \ + printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \ + "end: 0x%llx, size: 0x%llx\n", \ + __func__, __LINE__, type, dev_path(dev), index, base, base + size - 1, size) + +#define DEV_FUNC_ENTER(dev) \ + printk(BIOS_SPEW, "%s:%s:%d: ENTER (dev: %s)\n", \ + __FILE__, __func__, __LINE__, dev_path(dev)) + +#define DEV_FUNC_EXIT(dev) \ + printk(BIOS_SPEW, "%s:%s:%d: EXIT (dev: %s)\n", __FILE__, \ + __func__, __LINE__, dev_path(dev)) + +#define FUNC_ENTER() \ + printk(BIOS_SPEW, "%s:%s:%d: ENTER\n", __FILE__, __func__, __LINE__) + +#define FUNC_EXIT() \ + printk(BIOS_SPEW, "%s:%s:%d: EXIT\n", __FILE__, __func__, __LINE__) + +#endif diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index dc94dc6..bb86683 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -17,12 +17,11 @@
#include <arch/romstage.h> #include <cbmem.h> -#include <intelblocks/rtc.h> #include <console/console.h> #include <cpu/x86/mtrr.h> +#include <intelblocks/rtc.h> #include <soc/romstage.h> -#include <soc/soc_util.h> -#include "chip.h" +#include <soc/util.h>
asmlinkage void car_stage_entry(void) { @@ -57,27 +56,3 @@
run_postcar_phase(&pcf); } - -static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) -{ -} - -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -{ - const config_t *config = config_of_soc(); - FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - - mupd->FspmUpdVersion = FSP_UPD_VERSION; - - // ErrorLevel - 0 (disable) to 8 (verbose) - m_cfg->PcdFspMrcDebugPrintErrorLevel = 0; - m_cfg->PcdFspKtiDebugPrintErrorLevel = 0; - - soc_memory_init_params(m_cfg); - - mainboard_memory_init_params(mupd); - - m_cfg->VTdConfig.VTdSupport = config->vtd_support; - m_cfg->VTdConfig.CoherencySupport = config->coherency_support; - m_cfg->VTdConfig.ATS = config->ats_support; -} diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig new file mode 100644 index 0000000..1ce5ea6 --- /dev/null +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -0,0 +1,81 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 - 2020 Intel Corporation +## Copyright (C) 2019 - 2020 Facebook Inc +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if SOC_INTEL_SKYLAKE_SP + +config MAINBOARD_USES_FSP2_0 + bool + default y + +config USE_FSP2_0_DRIVER + def_bool y + depends on MAINBOARD_USES_FSP2_0 + select PLATFORM_USES_FSP2_0 + select UDK_2015_BINDING + select POSTCAR_CONSOLE + select POSTCAR_STAGE + +config FSP_HEADER_PATH + string "Location of FSP headers" + depends on MAINBOARD_USES_FSP2_0 + default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp" + +config MAX_SOCKET + int + default 2 + +# For 2S config, the number of cpus could be as high as +# 2 threads * 20 cores * 2 sockets +config MAX_CPUS + int + default 80 + +config PCR_BASE_ADDRESS + hex + default 0xfd000000 + help + This option allows you to select MMIO Base Address of sideband bus. + +config DCACHE_RAM_BASE + hex + default 0xfe800000 + +config DCACHE_RAM_SIZE + hex + default 0x200000 + +config DCACHE_BSP_STACK_SIZE + hex + default 0x10000 + +config CPU_MICROCODE_CBFS_LOC + hex + default 0xfff0fdc0 + +config CPU_MICROCODE_CBFS_LEN + hex + default 0x7C00 + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0xC000 + +config HEAP_SIZE + hex + default 0x80000 + +endif diff --git a/src/soc/intel/xeon_sp/skx/Makefile.inc b/src/soc/intel/xeon_sp/skx/Makefile.inc new file mode 100644 index 0000000..144a5c7 --- /dev/null +++ b/src/soc/intel/xeon_sp/skx/Makefile.inc @@ -0,0 +1,54 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 - 2020 Intel Corporation +## Copyright (C) 2019 - 2020 Facebook Inc +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ifeq ($(CONFIG_SOC_INTEL_SKYLAKE_SP),y) + +subdirs-y += ../../../../cpu/intel/microcode +subdirs-y += ../../../../cpu/intel/turbo +subdirs-y += ../../../../cpu/x86/lapic +subdirs-y += ../../../../cpu/x86/mtrr +subdirs-y += ../../../../cpu/x86/tsc +subdirs-y += ../../../../cpu/x86/cache +subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm + +bootblock-y += spi.c + +postcar-y += soc_util.c +postcar-y += spi.c + +romstage-y += soc_util.c +romstage-y += romstage.c +romstage-y += soc_util.c +romstage-y += spi.c +romstage-y += hob_display.c +romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c +romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c + +ramstage-y += soc_util.c +ramstage-y += chip.c +ramstage-y += soc_util.c +ramstage-y += lpc.c +ramstage-y += cpu.c +ramstage-y += spi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c +ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c +ramstage-y += hob_display.c + +CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/skx/include + +endif ## CONFIG_SOC_INTEL_SKYLAKE_SP diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c similarity index 99% rename from src/soc/intel/xeon_sp/acpi.c rename to src/soc/intel/xeon_sp/skx/acpi.c index 37dd420..6f9987f 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -881,7 +881,7 @@ acpi_slit_t *slit; acpi_dmar_t *dmar;
- const struct soc_intel_xeon_sp_config *const config = config_of(device); + const struct soc_intel_xeon_sp_skx_config *const config = config_of(device);
/* SRAT */ current = ALIGN(current, 8); diff --git a/src/soc/intel/xeon_sp/acpi/globalnvs.asl b/src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl similarity index 100% rename from src/soc/intel/xeon_sp/acpi/globalnvs.asl rename to src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl diff --git a/src/soc/intel/xeon_sp/acpi/iiostack.asl b/src/soc/intel/xeon_sp/skx/acpi/iiostack.asl similarity index 100% rename from src/soc/intel/xeon_sp/acpi/iiostack.asl rename to src/soc/intel/xeon_sp/skx/acpi/iiostack.asl diff --git a/src/soc/intel/xeon_sp/acpi/pci_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl similarity index 100% rename from src/soc/intel/xeon_sp/acpi/pci_irq.asl rename to src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl diff --git a/src/soc/intel/xeon_sp/acpi/uncore.asl b/src/soc/intel/xeon_sp/skx/acpi/uncore.asl similarity index 100% rename from src/soc/intel/xeon_sp/acpi/uncore.asl rename to src/soc/intel/xeon_sp/skx/acpi/uncore.asl diff --git a/src/soc/intel/xeon_sp/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl similarity index 100% rename from src/soc/intel/xeon_sp/acpi/uncore_irq.asl rename to src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl diff --git a/src/soc/intel/xeon_sp/chip.c b/src/soc/intel/xeon_sp/skx/chip.c similarity index 99% rename from src/soc/intel/xeon_sp/chip.c rename to src/soc/intel/xeon_sp/skx/chip.c index 832f98e..228ec42 100644 --- a/src/soc/intel/xeon_sp/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -591,8 +591,8 @@ mainboard_silicon_init_params(silupd); }
-struct chip_operations soc_intel_xeon_sp_ops = { - CHIP_NAME("Intel Xeon-SP SOC") +struct chip_operations soc_intel_xeon_sp_skx_ops = { + CHIP_NAME("Intel Skylake-SP") .enable_dev = soc_enable_dev, .init = soc_init, .final = soc_final diff --git a/src/soc/intel/xeon_sp/chip.h b/src/soc/intel/xeon_sp/skx/chip.h similarity index 95% rename from src/soc/intel/xeon_sp/chip.h rename to src/soc/intel/xeon_sp/skx/chip.h index 72f2445..de54fc0 100644 --- a/src/soc/intel/xeon_sp/chip.h +++ b/src/soc/intel/xeon_sp/skx/chip.h @@ -23,7 +23,7 @@ #include <intelblocks/cfg.h> #include <soc/irq.h>
-struct soc_intel_xeon_sp_config { +struct soc_intel_xeon_sp_skx_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config;
@@ -82,6 +82,6 @@
extern struct chip_operations soc_intel_xeon_sp_ops;
-typedef struct soc_intel_xeon_sp_config config_t; +typedef struct soc_intel_xeon_sp_skx_config config_t;
#endif diff --git a/src/soc/intel/xeon_sp/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c similarity index 100% rename from src/soc/intel/xeon_sp/cpu.c rename to src/soc/intel/xeon_sp/skx/cpu.c diff --git a/src/soc/intel/xeon_sp/hob_display.c b/src/soc/intel/xeon_sp/skx/hob_display.c similarity index 99% rename from src/soc/intel/xeon_sp/hob_display.c rename to src/soc/intel/xeon_sp/skx/hob_display.c index 1508011..65b54a6 100644 --- a/src/soc/intel/xeon_sp/hob_display.c +++ b/src/soc/intel/xeon_sp/skx/hob_display.c @@ -15,12 +15,12 @@ * GNU General Public License for more details. */
+#include <assert.h> #include <console/console.h> #include <fsp/util.h> -#include <lib.h> -#include <assert.h> #include <hob_iiouds.h> #include <hob_memmap.h> +#include <lib.h>
static const uint8_t fsp_hob_iio_uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; static const uint8_t fsp_hob_memmap_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/skx/include/soc/acpi.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/acpi.h rename to src/soc/intel/xeon_sp/skx/include/soc/acpi.h diff --git a/src/soc/intel/xeon_sp/include/soc/cpu.h b/src/soc/intel/xeon_sp/skx/include/soc/cpu.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/cpu.h rename to src/soc/intel/xeon_sp/skx/include/soc/cpu.h diff --git a/src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h b/src/soc/intel/xeon_sp/skx/include/soc/gpio_soc_defs.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h rename to src/soc/intel/xeon_sp/skx/include/soc/gpio_soc_defs.h diff --git a/src/soc/intel/xeon_sp/include/soc/irq.h b/src/soc/intel/xeon_sp/skx/include/soc/irq.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/irq.h rename to src/soc/intel/xeon_sp/skx/include/soc/irq.h diff --git a/src/soc/intel/xeon_sp/include/soc/msr.h b/src/soc/intel/xeon_sp/skx/include/soc/msr.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/msr.h rename to src/soc/intel/xeon_sp/skx/include/soc/msr.h diff --git a/src/soc/intel/xeon_sp/include/soc/nvs.h b/src/soc/intel/xeon_sp/skx/include/soc/nvs.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/nvs.h rename to src/soc/intel/xeon_sp/skx/include/soc/nvs.h diff --git a/src/soc/intel/xeon_sp/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/pci_devs.h rename to src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h diff --git a/src/soc/intel/xeon_sp/include/soc/pm.h b/src/soc/intel/xeon_sp/skx/include/soc/pm.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/pm.h rename to src/soc/intel/xeon_sp/skx/include/soc/pm.h diff --git a/src/soc/intel/xeon_sp/include/soc/pmc.h b/src/soc/intel/xeon_sp/skx/include/soc/pmc.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/pmc.h rename to src/soc/intel/xeon_sp/skx/include/soc/pmc.h diff --git a/src/soc/intel/xeon_sp/include/soc/ramstage.h b/src/soc/intel/xeon_sp/skx/include/soc/ramstage.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/ramstage.h rename to src/soc/intel/xeon_sp/skx/include/soc/ramstage.h diff --git a/src/soc/intel/xeon_sp/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h similarity index 60% rename from src/soc/intel/xeon_sp/include/soc/soc_util.h rename to src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index 8b5e1a2..735581a 100644 --- a/src/soc/intel/xeon_sp/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -21,31 +21,7 @@ #include <hob_iiouds.h> #include <hob_memmap.h> #include <arch/acpi.h> - -#define LOG_MEM_RESOURCE(type, dev, index, base_kb, size_kb) \ - printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \ - "end: 0x%llx, size_kb: 0x%llx\n", \ - __func__, __LINE__, type, dev_path(dev), index, (base_kb << 10), \ - (base_kb << 10) + (size_kb << 10) - 1, size_kb) - -#define LOG_IO_RESOURCE(type, dev, index, base, size) \ - printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \ - "end: 0x%llx, size: 0x%llx\n", \ - __func__, __LINE__, type, dev_path(dev), index, base, base + size - 1, size) - -#define DEV_FUNC_ENTER(dev) \ - printk(BIOS_SPEW, "%s:%s:%d: ENTER (dev: %s)\n", \ - __FILE__, __func__, __LINE__, dev_path(dev)) - -#define DEV_FUNC_EXIT(dev) \ - printk(BIOS_SPEW, "%s:%s:%d: EXIT (dev: %s)\n", __FILE__, \ - __func__, __LINE__, dev_path(dev)) - -#define FUNC_ENTER() \ - printk(BIOS_SPEW, "%s:%s:%d: ENTER\n", __FILE__, __func__, __LINE__) - -#define FUNC_EXIT() \ - printk(BIOS_SPEW, "%s:%s:%d: EXIT\n", __FILE__, __func__, __LINE__) +#include <soc/util.h>
struct iiostack_resource { uint8_t no_of_stacks; @@ -59,8 +35,6 @@
uint32_t pci_read_mmio_reg(int bus, uint32_t dev, uint32_t func, int offset);
-void get_stack_busnos(uint32_t *bus); -void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3); uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); void get_iiostack_info(struct iiostack_resource *info);
@@ -72,7 +46,6 @@ void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread);
-void unlock_pam_regions(void); void xeonsp_init_cpu_config(void); void set_bios_init_completion(void); void config_reset_cpl3_csrs(void); diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/skx/lpc.c similarity index 100% rename from src/soc/intel/xeon_sp/lpc.c rename to src/soc/intel/xeon_sp/skx/lpc.c diff --git a/src/soc/intel/xeon_sp/skx/romstage.c b/src/soc/intel/xeon_sp/skx/romstage.c new file mode 100644 index 0000000..a98fd07 --- /dev/null +++ b/src/soc/intel/xeon_sp/skx/romstage.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/romstage.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/x86/mtrr.h> +#include <intelblocks/rtc.h> +#include <soc/romstage.h> +#include <soc/soc_util.h> + +#include "chip.h" + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + const config_t *config = config_of_soc(); + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + mupd->FspmUpdVersion = FSP_UPD_VERSION; + + // ErrorLevel - 0 (disable) to 8 (verbose) + m_cfg->PcdFspMrcDebugPrintErrorLevel = 0; + m_cfg->PcdFspKtiDebugPrintErrorLevel = 0; + + mainboard_memory_init_params(mupd); + + m_cfg->VTdConfig.VTdSupport = config->vtd_support; + m_cfg->VTdConfig.CoherencySupport = config->coherency_support; + m_cfg->VTdConfig.ATS = config->ats_support; +} diff --git a/src/soc/intel/xeon_sp/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c similarity index 90% rename from src/soc/intel/xeon_sp/soc_util.c rename to src/soc/intel/xeon_sp/skx/soc_util.c index 6310bac..f6b581b 100644 --- a/src/soc/intel/xeon_sp/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -18,20 +18,17 @@ #include <assert.h> #include <commonlib/sort.h> #include <console/console.h> -#include <cpu/cpu.h> -#include <cpu/x86/msr.h> #include <delay.h> #include <device/pci.h> -#include <hob_iiouds.h> #include <intelblocks/cpulib.h> #include <intelblocks/pcr.h> -#include <soc/iomap.h> #include <soc/cpu.h> +#include <soc/iomap.h> #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> #include <soc/soc_util.h> -#include <stdlib.h> +#include <soc/util.h> #include <timer.h>
/* @@ -71,24 +68,6 @@ return addr; }
-/* - * Get Socket 0 CPUBUSNO(0), CPUBUSNO(1) PCI bus numbers UBOX (B0:D8:F2:Offset_CCh) - * TODO: D0h - */ -void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3) -{ - uint32_t bus = pci_io_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, - UBOX_DECS_FUNC), UBOX_DECS_CPUBUSNO_CSR); - if (bus0) - *bus0 = (bus & 0xff); - if (bus1) - *bus1 = (bus >> 8) & 0xff; - if (bus2) - *bus2 = (bus >> 16) & 0xff; - if (bus3) - *bus3 = (bus >> 24) & 0xff; -} - uint32_t top_of_32bit_ram(void) { uintptr_t mmcfg, tolm; @@ -155,42 +134,6 @@ return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; }
-/* bus needs to be of size 6 (MAX_IIO_STACK) */ -void get_stack_busnos(uint32_t *bus) -{ - uint32_t reg1, reg2; - - reg1 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC), - 0xcc); - reg2 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC), - 0xd0); - - for (int i = 0; i < 4; ++i) - bus[i] = ((reg1 >> (i * 8)) & 0xff); - for (int i = 0; i < 2; ++i) - bus[4+i] = ((reg2 >> (i * 8)) & 0xff); -} - -void unlock_pam_regions(void) -{ - uint32_t bus1 = 0; - uint32_t pam0123_unlock_dram = 0x33333330; - uint32_t pam456_unlock_dram = 0x00333333; - - get_cpubusnos(NULL, &bus1, NULL, NULL); - pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), - SAD_ALL_PAM0123_CSR, pam0123_unlock_dram); - pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), - SAD_ALL_PAM456_CSR, pam456_unlock_dram); - - uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, - SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR); - uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, - SAD_ALL_FUNC), SAD_ALL_PAM456_CSR); - printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n", - __FILE__, __func__, reg1, reg2); -} - /* return 1 if command timed out else 0 */ static uint32_t wait_for_bios_cmd_cpl(pci_devfn_t dev, uint32_t reg, uint32_t mask, uint32_t target) diff --git a/src/soc/intel/xeon_sp/spi.c b/src/soc/intel/xeon_sp/skx/spi.c similarity index 100% rename from src/soc/intel/xeon_sp/spi.c rename to src/soc/intel/xeon_sp/skx/spi.c diff --git a/src/soc/intel/xeon_sp/upd_display.c b/src/soc/intel/xeon_sp/skx/upd_display.c similarity index 100% rename from src/soc/intel/xeon_sp/upd_display.c rename to src/soc/intel/xeon_sp/skx/upd_display.c diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index adf3e3e..ebdd3d7 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -20,10 +20,13 @@ #include <cpu/x86/lapic.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <memrange.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> -#include <soc/soc_util.h> +#include <soc/util.h>
struct map_entry { uint32_t reg; diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c new file mode 100644 index 0000000..6f1e28d --- /dev/null +++ b/src/soc/intel/xeon_sp/util.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/pci.h> +#include <soc/pci_devs.h> +#include <soc/util.h> + +void get_stack_busnos(uint32_t *bus) +{ + uint32_t reg1, reg2; + + reg1 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC), + 0xcc); + reg2 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC), + 0xd0); + + for (int i = 0; i < 4; ++i) + bus[i] = ((reg1 >> (i * 8)) & 0xff); + for (int i = 0; i < 2; ++i) + bus[4+i] = ((reg2 >> (i * 8)) & 0xff); +} + +void unlock_pam_regions(void) +{ + uint32_t bus1 = 0; + uint32_t pam0123_unlock_dram = 0x33333330; + uint32_t pam456_unlock_dram = 0x00333333; + + get_cpubusnos(NULL, &bus1, NULL, NULL); + pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), + SAD_ALL_PAM0123_CSR, pam0123_unlock_dram); + pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), + SAD_ALL_PAM456_CSR, pam456_unlock_dram); + + uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, + SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR); + uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, + SAD_ALL_FUNC), SAD_ALL_PAM456_CSR); + printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n", + __FILE__, __func__, reg1, reg2); +} + +void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3) +{ + uint32_t bus = pci_io_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, + UBOX_DECS_FUNC), UBOX_DECS_CPUBUSNO_CSR); + if (bus0) + *bus0 = (bus & 0xff); + if (bus1) + *bus1 = (bus >> 8) & 0xff; + if (bus2) + *bus2 = (bus >> 16) & 0xff; + if (bus3) + *bus3 = (bus >> 24) & 0xff; +}