Attention is currently required from: Nico Huber, Paul Menzel, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47223 )
Change subject: nb/intel/haswell/pcie.c: Add missing pre-ASPM init ......................................................................
Patch Set 6:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/47223/comment/c6adfc08_470a5e9e PS6, Line 8:
Is this currently done by MRC? not done at all?
It wasn't done at all, IIRC. I can re-check.
Patchset:
PS6: a
File src/northbridge/intel/haswell/haswell.h:
https://review.coreboot.org/c/coreboot/+/47223/comment/42400452_cc15a169 PS6, Line 33: 0x11a
Datasheet says 0x114 (0x11a is status)? […]
Oops, well-spotted.
File src/northbridge/intel/haswell/pcie.c:
https://review.coreboot.org/c/coreboot/+/47223/comment/81ee10e9_ee7fabac PS6, Line 68: /* 75 watts power limit */
How to know if that's true for a board?
Devicetree, probably. i945 also has a FIXME.
https://review.coreboot.org/c/coreboot/+/47223/comment/b88302a8_0f74684a PS6, Line 85: pci_or_config32(dev, PEG_DCAP2, 1 << 19);
Hmm, BIOS spec says to lock (read, write) the original value.
What's the date of the BIOS spec? I can disable OBFF if need be.
https://review.coreboot.org/c/coreboot/+/47223/comment/6639f904_0ab94e35 PS6, Line 109: 0xac
Should be LCAP?
Yes, most likely