Aaron Durbin (adurbin@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3017
-gerrit
commit a7e6b0428be611e36c265b87e9ef9ef2c8bf1901 Author: Aaron Durbin adurbin@chromium.org Date: Wed Apr 3 09:56:57 2013 -0500
sandybridge: enable ROM caching
If ROM caching is selected the sandybridge chipset code will will enable ROM caching after all other CPU threads are brought up.
Change-Id: I3a57ba8753678146527ebf9547f5fbbd4f441f43 Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/northbridge/intel/sandybridge/northbridge.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index c39933f..b8022b8 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -25,6 +25,7 @@ #include <delay.h> #include <cpu/intel/model_206ax/model_206ax.h> #include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -486,6 +487,8 @@ static const struct pci_driver mc_driver_1 __pci_driver = { static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); + /* Enable ROM caching if option was selected. */ + x86_mtrr_enable_rom_caching(); }
static void cpu_bus_noop(device_t dev)