[coreboot-gerrit] [S] Change in coreboot[master]: mb/google/rex: Update USB2-C1 mapping

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70426 )

(

3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: mb/google/rex: Update USB2-C1 mapping
......................................................................

mb/google/rex: Update USB2-C1 mapping

This patch updates the USB2-C1 mapping from USB2 Port 4 to USB2 Port 1
as per latest Rex schematics dated 12/06/2022.

TEST=Hardward awaited.

Change-Id: Ifc82200e6eafcea7e820a96df81325f3c8849fd1
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70426
Reviewed-by: Eran Mitrani 
Reviewed-by: Eric Lai 
Reviewed-by: Ivy Jian 
Reviewed-by: Kapil Porwal 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/rex/variants/rex0/overridetree.cb
1 file changed, 30 insertions(+), 9 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Eric Lai: Looks good to me, approved
  Ivy Jian: Looks good to me, approved
  Eran Mitrani: Looks good to me, but someone else must approve
  Kapil Porwal: Looks good to me, approved

diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb
index 4724605..0c83341 100644
--- a/src/mainboard/google/rex/variants/rex0/overridetree.cb
+++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb
@@ -31,8 +31,8 @@

chip soc/intel/meteorlake

+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C1
    register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"	# USB2_C0
-	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C1
    register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 WWAN
    register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Camera
    register "usb2_ports[8]" = "USB2_PORT_MID(OC3)"		# Type-A Port A0
@@ -172,6 +172,13 @@
    		chip drivers/usb/acpi
    			device ref xhci_root_hub on
    				chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1 (DB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
    					register "desc" = ""USB2 Type-C Port C0 (MLB)""
    					register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
    					register "use_custom_pld" = "true"
@@ -179,13 +186,6 @@
    					device ref usb2_port2 on end
    				end
    				chip drivers/usb/acpi
-						register "desc" = ""USB2 Type-C Port C1 (DB)""
-						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
-						device ref usb2_port4 on end
-					end
-					chip drivers/usb/acpi
    					register "desc" = ""USB2 WWAN""
    					register "type" = "UPC_TYPE_INTERNAL"
    					device ref usb2_port5 on
@@ -536,7 +536,7 @@
    					device generic 0 alias conn0 on end
    				end
    				chip drivers/intel/pmc_mux/conn
-						use usb2_port4 as usb2_port
+						use usb2_port1 as usb2_port
    					use tcss_usb3_port3 as usb3_port
    					device generic 1 alias conn1 on end
    				end