[coreboot-gerrit] Change in coreboot[master]: [WIP] arch/riscv: Advance the instruction pointer after handling misa...

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Change subject: [WIP] arch/riscv: Advance the instruction pointer after handling misaligned load/store
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Patch Set 1:

(1 comment)

https://review.coreboot.org/#/c/28617/1/src/arch/riscv/misaligned.c
File src/arch/riscv/misaligned.c:

https://review.coreboot.org/#/c/28617/1/src/arch/riscv/misaligned.c@273
PS1, Line 273: 	write_csr(mepc, read_csr(mepc) + is_compressed? 2:4);
spaces required around that '?' (ctx:VxW)